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![Elaine Zhang](/assets/img/avatar_default.png)
Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
197 lines
4.7 KiB
C
197 lines
4.7 KiB
C
/*
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable fractional divider clock implementation.
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* Output rate = (m / n) * parent_rate.
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* Uses rational best approximation algorithm.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/rational.h>
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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unsigned long m, n;
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u32 val;
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u64 ret;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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m = (val & fd->mmask) >> fd->mshift;
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n = (val & fd->nmask) >> fd->nshift;
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if (!n || !m)
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return parent_rate;
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ret = (u64)parent_rate * m;
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do_div(ret, n);
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return ret;
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}
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static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate,
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unsigned long *m, unsigned long *n)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long scale;
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/*
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* Get rate closer to *parent_rate to guarantee there is no overflow
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* for m and n. In the result it will be the nearest rate left shifted
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* by (scale - fd->nwidth) bits.
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*/
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scale = fls_long(*parent_rate / rate - 1);
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if (scale > fd->nwidth)
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rate <<= scale - fd->nwidth;
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rational_best_approximation(rate, *parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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m, n);
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long m, n;
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u64 ret;
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if (!rate || rate >= *parent_rate)
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return *parent_rate;
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if (fd->approximation)
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fd->approximation(hw, rate, parent_rate, &m, &n);
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else
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clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
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ret = (u64)*parent_rate * m;
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do_div(ret, n);
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return ret;
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}
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static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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unsigned long m, n;
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u32 val;
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rational_best_approximation(rate, parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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&m, &n);
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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val &= ~(fd->mmask | fd->nmask);
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val |= (m << fd->mshift) | (n << fd->nshift);
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clk_writel(val, fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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return 0;
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}
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const struct clk_ops clk_fractional_divider_ops = {
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.recalc_rate = clk_fd_recalc_rate,
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.round_rate = clk_fd_round_rate,
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.set_rate = clk_fd_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
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struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_fractional_divider *fd;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_fractional_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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fd->reg = reg;
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fd->mshift = mshift;
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fd->mwidth = mwidth;
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fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
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fd->nshift = nshift;
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fd->nwidth = nwidth;
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fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
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fd->flags = clk_divider_flags;
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fd->lock = lock;
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fd->hw.init = &init;
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hw = &fd->hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(fd);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
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struct clk *clk_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
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reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
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lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
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void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
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{
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struct clk_fractional_divider *fd;
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fd = to_clk_fd(hw);
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clk_hw_unregister(hw);
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kfree(fd);
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}
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