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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 01:41:39 +00:00
![Romain Izard](/assets/img/avatar_default.png)
The clock speed displayed at boot in an information message was 500 kHz too high compared to its real value. As the value is not used anywhere, there is no functional impact. Fix the rounding formula to display the correct value. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1515418139-23276-4-git-send-email-daniel.lezcano@linaro.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
433 lines
12 KiB
C
433 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/syscore_ops.h>
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#include <linux/atmel_tc.h>
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/*
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* We're configured to use a specific TC block, one that's not hooked
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* up to external hardware, to provide a time solution:
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*
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* - Two channels combine to create a free-running 32 bit counter
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* with a base rate of 5+ MHz, packaged as a clocksource (with
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* resolution better than 200 nsec).
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* - Some chips support 32 bit counter. A single channel is used for
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* this 32 bit free-running counter. the second channel is not used.
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*
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* - The third channel may be used to provide a 16-bit clockevent
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* source, used in either periodic or oneshot mode. This runs
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* at 32 KiHZ, and can handle delays of up to two seconds.
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*
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* A boot clocksource and clockevent source are also currently needed,
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* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
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* this code can be used when init_timers() is called, well before most
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* devices are set up. (Some low end AT91 parts, which can run uClinux,
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* have only the timers in one TC block... they currently don't support
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* the tclib code, because of that initialization issue.)
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*
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* REVISIT behavior during system suspend states... we should disable
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* all clocks and save the power. Easily done for clockevent devices,
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* but clocksources won't necessarily get the needed notifications.
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* For deeper system sleep states, this will be mandatory...
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*/
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static void __iomem *tcaddr;
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static struct
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{
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u32 cmr;
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u32 imr;
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u32 rc;
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bool clken;
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} tcb_cache[3];
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static u32 bmr_cache;
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static u64 tc_get_cycles(struct clocksource *cs)
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{
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unsigned long flags;
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u32 lower, upper;
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raw_local_irq_save(flags);
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do {
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upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
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lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
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} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
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raw_local_irq_restore(flags);
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return (upper << 16) | lower;
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}
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static u64 tc_get_cycles32(struct clocksource *cs)
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{
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return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
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}
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void tc_clksrc_suspend(struct clocksource *cs)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
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tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
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tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
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tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
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tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
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ATMEL_TC_CLKSTA);
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}
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bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
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}
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void tc_clksrc_resume(struct clocksource *cs)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
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/* Restore registers for the channel, RA and RB are not used */
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writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
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writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
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writel(0, tcaddr + ATMEL_TC_REG(i, RA));
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writel(0, tcaddr + ATMEL_TC_REG(i, RB));
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/* Disable all the interrupts */
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writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
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/* Reenable interrupts that were enabled before suspending */
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writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
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/* Start the clock if it was used */
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if (tcb_cache[i].clken)
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
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}
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/* Dual channel, chain channels */
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writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
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/* Finally, trigger all the channels*/
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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}
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static struct clocksource clksrc = {
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.name = "tcb_clksrc",
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.rating = 200,
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.read = tc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.suspend = tc_clksrc_suspend,
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.resume = tc_clksrc_resume,
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};
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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struct tc_clkevt_device {
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struct clock_event_device clkevt;
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struct clk *clk;
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void __iomem *regs;
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};
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static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
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{
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return container_of(clkevt, struct tc_clkevt_device, clkevt);
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}
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/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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* because using one of the divided clocks would usually mean the
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* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
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*
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* A divided clock could be good for high resolution timers, since
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* 30.5 usec resolution can seem "low".
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*/
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static u32 timer_clock;
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static int tc_shutdown(struct clock_event_device *d)
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{
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struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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void __iomem *regs = tcd->regs;
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writel(0xff, regs + ATMEL_TC_REG(2, IDR));
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writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
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if (!clockevent_state_detached(d))
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clk_disable(tcd->clk);
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return 0;
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}
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static int tc_set_oneshot(struct clock_event_device *d)
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{
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struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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void __iomem *regs = tcd->regs;
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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tc_shutdown(d);
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clk_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and stop */
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writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
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ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
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writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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/* set_next_event() configures and starts the timer */
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return 0;
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}
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static int tc_set_periodic(struct clock_event_device *d)
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{
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struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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void __iomem *regs = tcd->regs;
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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tc_shutdown(d);
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/* By not making the gentime core emulate periodic mode on top
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* of oneshot, we get lower overhead and improved accuracy.
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*/
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clk_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and restart */
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writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
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regs + ATMEL_TC_REG(2, CMR));
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writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
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/* Enable clock and interrupts on RC compare */
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writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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/* go go gadget! */
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writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
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ATMEL_TC_REG(2, CCR));
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return 0;
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}
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static int tc_next_event(unsigned long delta, struct clock_event_device *d)
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{
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writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
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/* go go gadget! */
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writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
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tcaddr + ATMEL_TC_REG(2, CCR));
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return 0;
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}
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static struct tc_clkevt_device clkevt = {
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.clkevt = {
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.name = "tc_clkevt",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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/* Should be lower than at91rm9200's system timer */
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.rating = 125,
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.set_next_event = tc_next_event,
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.set_state_shutdown = tc_shutdown,
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.set_state_periodic = tc_set_periodic,
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.set_state_oneshot = tc_set_oneshot,
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},
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};
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static irqreturn_t ch2_irq(int irq, void *handle)
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{
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struct tc_clkevt_device *dev = handle;
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unsigned int sr;
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sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
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if (sr & ATMEL_TC_CPCS) {
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dev->clkevt.event_handler(&dev->clkevt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
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{
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int ret;
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struct clk *t2_clk = tc->clk[2];
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int irq = tc->irq[2];
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ret = clk_prepare_enable(tc->slow_clk);
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if (ret)
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return ret;
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/* try to enable t2 clk to avoid future errors in mode change */
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ret = clk_prepare_enable(t2_clk);
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if (ret) {
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clk_disable_unprepare(tc->slow_clk);
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return ret;
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}
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clk_disable(t2_clk);
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clkevt.regs = tc->regs;
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clkevt.clk = t2_clk;
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timer_clock = clk32k_divisor_idx;
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clkevt.clkevt.cpumask = cpumask_of(0);
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ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
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if (ret) {
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clk_unprepare(t2_clk);
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clk_disable_unprepare(tc->slow_clk);
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return ret;
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}
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clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
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return ret;
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}
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#else /* !CONFIG_GENERIC_CLOCKEVENTS */
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static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
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{
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/* NOTHING */
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return 0;
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}
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#endif
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static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
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{
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/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
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writel(mck_divisor_idx /* likely divide-by-8 */
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| ATMEL_TC_WAVE
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| ATMEL_TC_WAVESEL_UP /* free-run */
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| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
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| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
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tcaddr + ATMEL_TC_REG(0, CMR));
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writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
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writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
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writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
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/* channel 1: waveform mode, input TIOA0 */
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writel(ATMEL_TC_XC1 /* input: TIOA0 */
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| ATMEL_TC_WAVE
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| ATMEL_TC_WAVESEL_UP, /* free-run */
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tcaddr + ATMEL_TC_REG(1, CMR));
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writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
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/* chain channel 0 to channel 1*/
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writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
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/* then reset all the timers */
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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}
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static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
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{
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/* channel 0: waveform mode, input mclk/8 */
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writel(mck_divisor_idx /* likely divide-by-8 */
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| ATMEL_TC_WAVE
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| ATMEL_TC_WAVESEL_UP, /* free-run */
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tcaddr + ATMEL_TC_REG(0, CMR));
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writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
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/* then reset all the timers */
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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}
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static int __init tcb_clksrc_init(void)
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{
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static char bootinfo[] __initdata
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= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
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struct platform_device *pdev;
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struct atmel_tc *tc;
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struct clk *t0_clk;
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u32 rate, divided_rate = 0;
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int best_divisor_idx = -1;
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int clk32k_divisor_idx = -1;
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int i;
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int ret;
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tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
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if (!tc) {
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pr_debug("can't alloc TC for clocksource\n");
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return -ENODEV;
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}
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tcaddr = tc->regs;
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pdev = tc->pdev;
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t0_clk = tc->clk[0];
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ret = clk_prepare_enable(t0_clk);
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if (ret) {
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pr_debug("can't enable T0 clk\n");
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goto err_free_tc;
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}
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/* How fast will we be counting? Pick something over 5 MHz. */
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rate = (u32) clk_get_rate(t0_clk);
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for (i = 0; i < 5; i++) {
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unsigned divisor = atmel_tc_divisors[i];
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unsigned tmp;
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/* remember 32 KiHz clock for later */
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if (!divisor) {
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clk32k_divisor_idx = i;
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continue;
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}
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tmp = rate / divisor;
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pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
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if (best_divisor_idx > 0) {
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if (tmp < 5 * 1000 * 1000)
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continue;
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}
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divided_rate = tmp;
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best_divisor_idx = i;
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}
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printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
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divided_rate / 1000000,
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((divided_rate % 1000000) + 500) / 1000);
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if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
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/* use apropriate function to read 32 bit counter */
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clksrc.read = tc_get_cycles32;
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/* setup ony channel 0 */
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tcb_setup_single_chan(tc, best_divisor_idx);
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} else {
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/* tclib will give us three clocks no matter what the
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* underlying platform supports.
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*/
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ret = clk_prepare_enable(tc->clk[1]);
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if (ret) {
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pr_debug("can't enable T1 clk\n");
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goto err_disable_t0;
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}
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/* setup both channel 0 & 1 */
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tcb_setup_dual_chan(tc, best_divisor_idx);
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}
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/* and away we go! */
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ret = clocksource_register_hz(&clksrc, divided_rate);
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if (ret)
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goto err_disable_t1;
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/* channel 2: periodic and oneshot timer support */
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ret = setup_clkevents(tc, clk32k_divisor_idx);
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if (ret)
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goto err_unregister_clksrc;
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return 0;
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err_unregister_clksrc:
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clocksource_unregister(&clksrc);
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err_disable_t1:
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if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
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clk_disable_unprepare(tc->clk[1]);
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err_disable_t0:
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clk_disable_unprepare(t0_clk);
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err_free_tc:
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atmel_tc_free(tc);
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return ret;
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}
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arch_initcall(tcb_clksrc_init);
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