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![Andy Shevchenko](/assets/img/avatar_default.png)
It appears that some code lines raise the question why they are needed and how they are participated in the calculus of the resulting values. Document this in a form of the top comment in the module file. Reported-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210812170025.67074-4-andriy.shevchenko@linux.intel.com [sboyd@kernel.org: Remove "die" as it isn't relevant] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
259 lines
6.3 KiB
C
259 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014 Intel Corporation
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*
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* Adjustable fractional divider clock implementation.
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* Uses rational best approximation algorithm.
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*
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* Output is calculated as
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*
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* rate = (m / n) * parent_rate (1)
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*
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* This is useful when we have a prescaler block which asks for
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* m (numerator) and n (denominator) values to be provided to satisfy
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* the (1) as much as possible.
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*
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* Since m and n have the limitation by a range, e.g.
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*
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* n >= 1, n < N_width, where N_width = 2^nwidth (2)
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*
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* for some cases the output may be saturated. Hence, from (1) and (2),
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* assuming the worst case when m = 1, the inequality
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*
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* floor(log2(parent_rate / rate)) <= nwidth (3)
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*
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* may be derived. Thus, in cases when
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*
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* (parent_rate / rate) >> N_width (4)
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*
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* we might scale up the rate by 2^scale (see the description of
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* CLK_FRAC_DIVIDER_POWER_OF_TWO_PS for additional information), where
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*
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* scale = floor(log2(parent_rate / rate)) - nwidth (5)
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*
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* and assume that the IP, that needs m and n, has also its own
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* prescaler, which is capable to divide by 2^scale. In this way
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* we get the denominator to satisfy the desired range (2) and
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* at the same time much much better result of m and n than simple
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* saturated values.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/rational.h>
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#include "clk-fractional-divider.h"
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static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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return ioread32be(fd->reg);
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return readl(fd->reg);
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}
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static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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iowrite32be(val, fd->reg);
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else
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writel(val, fd->reg);
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}
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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unsigned long m, n;
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u32 val;
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u64 ret;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_fd_readl(fd);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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m = (val & fd->mmask) >> fd->mshift;
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n = (val & fd->nmask) >> fd->nshift;
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m++;
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n++;
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}
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if (!n || !m)
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return parent_rate;
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ret = (u64)parent_rate * m;
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do_div(ret, n);
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return ret;
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}
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void clk_fractional_divider_general_approximation(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate,
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unsigned long *m, unsigned long *n)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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/*
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* Get rate closer to *parent_rate to guarantee there is no overflow
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* for m and n. In the result it will be the nearest rate left shifted
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* by (scale - fd->nwidth) bits.
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*
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* For the detailed explanation see the top comment in this file.
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*/
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if (fd->flags & CLK_FRAC_DIVIDER_POWER_OF_TWO_PS) {
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unsigned long scale = fls_long(*parent_rate / rate - 1);
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if (scale > fd->nwidth)
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rate <<= scale - fd->nwidth;
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}
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rational_best_approximation(rate, *parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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m, n);
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long m, n;
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u64 ret;
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if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
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return *parent_rate;
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if (fd->approximation)
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fd->approximation(hw, rate, parent_rate, &m, &n);
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else
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clk_fractional_divider_general_approximation(hw, rate, parent_rate, &m, &n);
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ret = (u64)*parent_rate * m;
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do_div(ret, n);
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return ret;
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}
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static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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unsigned long m, n;
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u32 val;
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rational_best_approximation(rate, parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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&m, &n);
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m--;
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n--;
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}
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_fd_readl(fd);
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val &= ~(fd->mmask | fd->nmask);
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val |= (m << fd->mshift) | (n << fd->nshift);
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clk_fd_writel(fd, val);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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return 0;
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}
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const struct clk_ops clk_fractional_divider_ops = {
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.recalc_rate = clk_fd_recalc_rate,
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.round_rate = clk_fd_round_rate,
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.set_rate = clk_fd_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
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struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_fractional_divider *fd;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_fractional_divider_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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fd->reg = reg;
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fd->mshift = mshift;
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fd->mwidth = mwidth;
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fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
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fd->nshift = nshift;
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fd->nwidth = nwidth;
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fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
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fd->flags = clk_divider_flags;
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fd->lock = lock;
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fd->hw.init = &init;
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hw = &fd->hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(fd);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
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struct clk *clk_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
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reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
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lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
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void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
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{
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struct clk_fractional_divider *fd;
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fd = to_clk_fd(hw);
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clk_hw_unregister(hw);
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kfree(fd);
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}
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