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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Iwona Winiarska](/assets/img/avatar_default.png)
The gpio-aspeed driver implements an irq_chip which need to be invoked from hardirq context. Since spin_lock() can sleep with PREEMPT_RT, it is no longer legal to invoke it while interrupts are disabled. This also causes lockdep to complain about: [ 0.649797] [ BUG: Invalid wait context ] because aspeed_gpio.lock (spin_lock_t) is taken under irq_desc.lock (raw_spinlock_t). Let's use of raw_spinlock_t instead of spinlock_t. Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
1251 lines
32 KiB
C
1251 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015 IBM Corp.
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*
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* Joel Stanley <joel@jms.id.au>
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*/
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#include <asm/div64.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/aspeed.h>
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#include <linux/hashtable.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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/*
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* These two headers aren't meant to be used by GPIO drivers. We need
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* them in order to access gpio_chip_hwgpio() which we need to implement
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* the aspeed specific API which allows the coprocessor to request
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* access to some GPIOs and to arbitrate between coprocessor and ARM.
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*/
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#include <linux/gpio/consumer.h>
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#include "gpiolib.h"
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struct aspeed_bank_props {
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unsigned int bank;
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u32 input;
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u32 output;
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};
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struct aspeed_gpio_config {
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unsigned int nr_gpios;
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const struct aspeed_bank_props *props;
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};
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/*
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* @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
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* @timer_users: Tracks the number of users for each timer
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*
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* The @timer_users has four elements but the first element is unused. This is
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* to simplify accounting and indexing, as a zero value in @offset_timer
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* represents disabled debouncing for the GPIO. Any other value for an element
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* of @offset_timer is used as an index into @timer_users. This behaviour of
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* the zero value aligns with the behaviour of zero built from the timer
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* configuration registers (i.e. debouncing is disabled).
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*/
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struct aspeed_gpio {
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struct gpio_chip chip;
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struct irq_chip irqc;
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raw_spinlock_t lock;
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void __iomem *base;
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int irq;
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const struct aspeed_gpio_config *config;
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u8 *offset_timer;
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unsigned int timer_users[4];
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struct clk *clk;
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u32 *dcache;
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u8 *cf_copro_bankmap;
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};
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struct aspeed_gpio_bank {
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uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
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* +4: Rd/Wr: Direction (0=in, 1=out)
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*/
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uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
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uint16_t irq_regs;
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uint16_t debounce_regs;
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uint16_t tolerance_regs;
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uint16_t cmdsrc_regs;
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const char names[4][3];
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};
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/*
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* Note: The "value" register returns the input value sampled on the
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* line even when the GPIO is configured as an output. Since
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* that input goes through synchronizers, writing, then reading
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* back may not return the written value right away.
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*
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* The "rdata" register returns the content of the write latch
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* and thus can be used to read back what was last written
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* reliably.
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*/
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static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
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static const struct aspeed_gpio_copro_ops *copro_ops;
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static void *copro_data;
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static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
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{
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.val_regs = 0x0000,
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.rdata_reg = 0x00c0,
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.irq_regs = 0x0008,
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.debounce_regs = 0x0040,
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.tolerance_regs = 0x001c,
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.cmdsrc_regs = 0x0060,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x0020,
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.rdata_reg = 0x00c4,
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.irq_regs = 0x0028,
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.debounce_regs = 0x0048,
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.tolerance_regs = 0x003c,
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.cmdsrc_regs = 0x0068,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0070,
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.rdata_reg = 0x00c8,
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.irq_regs = 0x0098,
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.debounce_regs = 0x00b0,
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.tolerance_regs = 0x00ac,
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.cmdsrc_regs = 0x0090,
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.names = { "I", "J", "K", "L" },
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},
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{
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.val_regs = 0x0078,
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.rdata_reg = 0x00cc,
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.irq_regs = 0x00e8,
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.debounce_regs = 0x0100,
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.tolerance_regs = 0x00fc,
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.cmdsrc_regs = 0x00e0,
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.names = { "M", "N", "O", "P" },
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},
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{
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.val_regs = 0x0080,
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.rdata_reg = 0x00d0,
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.irq_regs = 0x0118,
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.debounce_regs = 0x0130,
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.tolerance_regs = 0x012c,
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.cmdsrc_regs = 0x0110,
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.names = { "Q", "R", "S", "T" },
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},
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{
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.val_regs = 0x0088,
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.rdata_reg = 0x00d4,
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.irq_regs = 0x0148,
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.debounce_regs = 0x0160,
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.tolerance_regs = 0x015c,
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.cmdsrc_regs = 0x0140,
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.names = { "U", "V", "W", "X" },
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},
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{
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.val_regs = 0x01E0,
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.rdata_reg = 0x00d8,
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.irq_regs = 0x0178,
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.debounce_regs = 0x0190,
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.tolerance_regs = 0x018c,
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.cmdsrc_regs = 0x0170,
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.names = { "Y", "Z", "AA", "AB" },
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},
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{
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.val_regs = 0x01e8,
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.rdata_reg = 0x00dc,
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.irq_regs = 0x01a8,
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.debounce_regs = 0x01c0,
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.tolerance_regs = 0x01bc,
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.cmdsrc_regs = 0x01a0,
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.names = { "AC", "", "", "" },
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},
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};
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enum aspeed_gpio_reg {
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reg_val,
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reg_rdata,
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reg_dir,
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reg_irq_enable,
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reg_irq_type0,
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reg_irq_type1,
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reg_irq_type2,
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reg_irq_status,
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reg_debounce_sel1,
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reg_debounce_sel2,
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reg_tolerance,
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reg_cmdsrc0,
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reg_cmdsrc1,
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};
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#define GPIO_VAL_VALUE 0x00
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#define GPIO_VAL_DIR 0x04
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
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#define GPIO_IRQ_TYPE1 0x08
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#define GPIO_IRQ_TYPE2 0x0c
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#define GPIO_IRQ_STATUS 0x10
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#define GPIO_DEBOUNCE_SEL1 0x00
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#define GPIO_DEBOUNCE_SEL2 0x04
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#define GPIO_CMDSRC_0 0x00
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#define GPIO_CMDSRC_1 0x04
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#define GPIO_CMDSRC_ARM 0
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#define GPIO_CMDSRC_LPC 1
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#define GPIO_CMDSRC_COLDFIRE 2
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#define GPIO_CMDSRC_RESERVED 3
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/* This will be resolved at compile time */
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static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
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const struct aspeed_gpio_bank *bank,
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const enum aspeed_gpio_reg reg)
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{
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switch (reg) {
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case reg_val:
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return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
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case reg_rdata:
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return gpio->base + bank->rdata_reg;
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case reg_dir:
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return gpio->base + bank->val_regs + GPIO_VAL_DIR;
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case reg_irq_enable:
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return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
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case reg_irq_type0:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
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case reg_irq_type1:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
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case reg_irq_type2:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
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case reg_irq_status:
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return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
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case reg_debounce_sel1:
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return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
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case reg_debounce_sel2:
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return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
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case reg_tolerance:
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return gpio->base + bank->tolerance_regs;
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case reg_cmdsrc0:
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return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
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case reg_cmdsrc1:
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return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
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}
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BUG();
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}
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_OFFSET(x) ((x) & 0x1f)
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
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#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
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#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
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#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
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static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
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return &aspeed_gpio_banks[bank];
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}
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static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
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{
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return !(props->input || props->output);
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}
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static inline const struct aspeed_bank_props *find_bank_props(
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struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = gpio->config->props;
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while (!is_bank_props_sentinel(props)) {
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if (props->bank == GPIO_BANK(offset))
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return props;
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props++;
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}
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return NULL;
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}
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static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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unsigned int group = GPIO_OFFSET(offset) / 8;
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return bank->names[group][0] != '\0' &&
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(!props || ((props->input | props->output) & GPIO_BIT(offset)));
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}
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static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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return !props || (props->input & GPIO_BIT(offset));
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}
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#define have_irq(g, o) have_input((g), (o))
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#define have_debounce(g, o) have_input((g), (o))
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static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
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{
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const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
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return !props || (props->output & GPIO_BIT(offset));
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}
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static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
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const struct aspeed_gpio_bank *bank,
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int bindex, int cmdsrc)
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{
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void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
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void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
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u32 bit, reg;
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/*
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* Each register controls 4 banks, so take the bottom 2
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* bits of the bank index, and use them to select the
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* right control bit (0, 8, 16 or 24).
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*/
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bit = BIT((bindex & 3) << 3);
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/* Source 1 first to avoid illegal 11 combination */
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reg = ioread32(c1);
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if (cmdsrc & 2)
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reg |= bit;
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else
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reg &= ~bit;
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iowrite32(reg, c1);
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/* Then Source 0 */
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reg = ioread32(c0);
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if (cmdsrc & 1)
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reg |= bit;
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else
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reg &= ~bit;
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iowrite32(reg, c0);
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}
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static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
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unsigned int offset)
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{
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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if (!copro_ops || !gpio->cf_copro_bankmap)
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return false;
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if (!gpio->cf_copro_bankmap[offset >> 3])
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return false;
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if (!copro_ops->request_access)
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return false;
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/* Pause the coprocessor */
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copro_ops->request_access(copro_data);
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/* Change command source back to ARM */
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aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
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/* Update cache */
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gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
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return true;
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}
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static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
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unsigned int offset)
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{
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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if (!copro_ops || !gpio->cf_copro_bankmap)
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return;
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if (!gpio->cf_copro_bankmap[offset >> 3])
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return;
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if (!copro_ops->release_access)
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return;
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/* Change command source back to ColdFire */
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aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
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GPIO_CMDSRC_COLDFIRE);
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/* Restart the coprocessor */
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copro_ops->release_access(copro_data);
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}
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static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
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}
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static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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void __iomem *addr;
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u32 reg;
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addr = bank_reg(gpio, bank, reg_val);
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reg = gpio->dcache[GPIO_BANK(offset)];
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if (val)
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reg |= GPIO_BIT(offset);
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else
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reg &= ~GPIO_BIT(offset);
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gpio->dcache[GPIO_BANK(offset)] = reg;
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iowrite32(reg, addr);
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}
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static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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bool copro;
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raw_spin_lock_irqsave(&gpio->lock, flags);
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copro = aspeed_gpio_copro_request(gpio, offset);
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__aspeed_gpio_set(gc, offset, val);
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if (copro)
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aspeed_gpio_copro_release(gpio, offset);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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void __iomem *addr = bank_reg(gpio, bank, reg_dir);
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unsigned long flags;
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bool copro;
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u32 reg;
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if (!have_input(gpio, offset))
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return -ENOTSUPP;
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raw_spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(addr);
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reg &= ~GPIO_BIT(offset);
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copro = aspeed_gpio_copro_request(gpio, offset);
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iowrite32(reg, addr);
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if (copro)
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aspeed_gpio_copro_release(gpio, offset);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_gpio_dir_out(struct gpio_chip *gc,
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unsigned int offset, int val)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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void __iomem *addr = bank_reg(gpio, bank, reg_dir);
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unsigned long flags;
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bool copro;
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u32 reg;
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if (!have_output(gpio, offset))
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return -ENOTSUPP;
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raw_spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(addr);
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reg |= GPIO_BIT(offset);
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copro = aspeed_gpio_copro_request(gpio, offset);
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__aspeed_gpio_set(gc, offset, val);
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iowrite32(reg, addr);
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if (copro)
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aspeed_gpio_copro_release(gpio, offset);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
|
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
if (!have_input(gpio, offset))
|
|
return GPIO_LINE_DIRECTION_OUT;
|
|
|
|
if (!have_output(gpio, offset))
|
|
return GPIO_LINE_DIRECTION_IN;
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
|
|
val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
|
|
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
|
|
return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
|
|
}
|
|
|
|
static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
|
|
struct aspeed_gpio **gpio,
|
|
const struct aspeed_gpio_bank **bank,
|
|
u32 *bit, int *offset)
|
|
{
|
|
struct aspeed_gpio *internal;
|
|
|
|
*offset = irqd_to_hwirq(d);
|
|
|
|
internal = irq_data_get_irq_chip_data(d);
|
|
|
|
/* This might be a bit of a questionable place to check */
|
|
if (!have_irq(internal, *offset))
|
|
return -ENOTSUPP;
|
|
|
|
*gpio = internal;
|
|
*bank = to_bank(*offset);
|
|
*bit = GPIO_BIT(*offset);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void aspeed_gpio_irq_ack(struct irq_data *d)
|
|
{
|
|
const struct aspeed_gpio_bank *bank;
|
|
struct aspeed_gpio *gpio;
|
|
unsigned long flags;
|
|
void __iomem *status_addr;
|
|
int rc, offset;
|
|
bool copro;
|
|
u32 bit;
|
|
|
|
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
|
if (rc)
|
|
return;
|
|
|
|
status_addr = bank_reg(gpio, bank, reg_irq_status);
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
copro = aspeed_gpio_copro_request(gpio, offset);
|
|
|
|
iowrite32(bit, status_addr);
|
|
|
|
if (copro)
|
|
aspeed_gpio_copro_release(gpio, offset);
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
}
|
|
|
|
static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
|
|
{
|
|
const struct aspeed_gpio_bank *bank;
|
|
struct aspeed_gpio *gpio;
|
|
unsigned long flags;
|
|
u32 reg, bit;
|
|
void __iomem *addr;
|
|
int rc, offset;
|
|
bool copro;
|
|
|
|
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
|
if (rc)
|
|
return;
|
|
|
|
addr = bank_reg(gpio, bank, reg_irq_enable);
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
copro = aspeed_gpio_copro_request(gpio, offset);
|
|
|
|
reg = ioread32(addr);
|
|
if (set)
|
|
reg |= bit;
|
|
else
|
|
reg &= ~bit;
|
|
iowrite32(reg, addr);
|
|
|
|
if (copro)
|
|
aspeed_gpio_copro_release(gpio, offset);
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
}
|
|
|
|
static void aspeed_gpio_irq_mask(struct irq_data *d)
|
|
{
|
|
aspeed_gpio_irq_set_mask(d, false);
|
|
}
|
|
|
|
static void aspeed_gpio_irq_unmask(struct irq_data *d)
|
|
{
|
|
aspeed_gpio_irq_set_mask(d, true);
|
|
}
|
|
|
|
static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
u32 type0 = 0;
|
|
u32 type1 = 0;
|
|
u32 type2 = 0;
|
|
u32 bit, reg;
|
|
const struct aspeed_gpio_bank *bank;
|
|
irq_flow_handler_t handler;
|
|
struct aspeed_gpio *gpio;
|
|
unsigned long flags;
|
|
void __iomem *addr;
|
|
int rc, offset;
|
|
bool copro;
|
|
|
|
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
|
if (rc)
|
|
return -EINVAL;
|
|
|
|
switch (type & IRQ_TYPE_SENSE_MASK) {
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
type2 |= bit;
|
|
fallthrough;
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
type0 |= bit;
|
|
fallthrough;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
handler = handle_edge_irq;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
type0 |= bit;
|
|
fallthrough;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
type1 |= bit;
|
|
handler = handle_level_irq;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
copro = aspeed_gpio_copro_request(gpio, offset);
|
|
|
|
addr = bank_reg(gpio, bank, reg_irq_type0);
|
|
reg = ioread32(addr);
|
|
reg = (reg & ~bit) | type0;
|
|
iowrite32(reg, addr);
|
|
|
|
addr = bank_reg(gpio, bank, reg_irq_type1);
|
|
reg = ioread32(addr);
|
|
reg = (reg & ~bit) | type1;
|
|
iowrite32(reg, addr);
|
|
|
|
addr = bank_reg(gpio, bank, reg_irq_type2);
|
|
reg = ioread32(addr);
|
|
reg = (reg & ~bit) | type2;
|
|
iowrite32(reg, addr);
|
|
|
|
if (copro)
|
|
aspeed_gpio_copro_release(gpio, offset);
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
|
|
irq_set_handler_locked(d, handler);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void aspeed_gpio_irq_handler(struct irq_desc *desc)
|
|
{
|
|
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
|
struct irq_chip *ic = irq_desc_get_chip(desc);
|
|
struct aspeed_gpio *data = gpiochip_get_data(gc);
|
|
unsigned int i, p, banks;
|
|
unsigned long reg;
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
|
|
|
chained_irq_enter(ic, desc);
|
|
|
|
banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
|
|
for (i = 0; i < banks; i++) {
|
|
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
|
|
|
|
reg = ioread32(bank_reg(data, bank, reg_irq_status));
|
|
|
|
for_each_set_bit(p, ®, 32)
|
|
generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
|
|
}
|
|
|
|
chained_irq_exit(ic, desc);
|
|
}
|
|
|
|
static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
|
|
unsigned long *valid_mask,
|
|
unsigned int ngpios)
|
|
{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
|
const struct aspeed_bank_props *props = gpio->config->props;
|
|
|
|
while (!is_bank_props_sentinel(props)) {
|
|
unsigned int offset;
|
|
const unsigned long int input = props->input;
|
|
|
|
/* Pretty crummy approach, but similar to GPIO core */
|
|
for_each_clear_bit(offset, &input, 32) {
|
|
unsigned int i = props->bank * 32 + offset;
|
|
|
|
if (i >= gpio->chip.ngpio)
|
|
break;
|
|
|
|
clear_bit(i, valid_mask);
|
|
}
|
|
|
|
props++;
|
|
}
|
|
}
|
|
|
|
static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
|
|
unsigned int offset, bool enable)
|
|
{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
unsigned long flags;
|
|
void __iomem *treg;
|
|
bool copro;
|
|
u32 val;
|
|
|
|
treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
copro = aspeed_gpio_copro_request(gpio, offset);
|
|
|
|
val = readl(treg);
|
|
|
|
if (enable)
|
|
val |= GPIO_BIT(offset);
|
|
else
|
|
val &= ~GPIO_BIT(offset);
|
|
|
|
writel(val, treg);
|
|
|
|
if (copro)
|
|
aspeed_gpio_copro_release(gpio, offset);
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
|
|
{
|
|
if (!have_gpio(gpiochip_get_data(chip), offset))
|
|
return -ENODEV;
|
|
|
|
return pinctrl_gpio_request(chip->base + offset);
|
|
}
|
|
|
|
static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
|
|
{
|
|
pinctrl_gpio_free(chip->base + offset);
|
|
}
|
|
|
|
static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
|
|
u32 *cycles)
|
|
{
|
|
u64 rate;
|
|
u64 n;
|
|
u32 r;
|
|
|
|
rate = clk_get_rate(gpio->clk);
|
|
if (!rate)
|
|
return -ENOTSUPP;
|
|
|
|
n = rate * usecs;
|
|
r = do_div(n, 1000000);
|
|
|
|
if (n >= U32_MAX)
|
|
return -ERANGE;
|
|
|
|
/* At least as long as the requested time */
|
|
*cycles = n + (!!r);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Call under gpio->lock */
|
|
static int register_allocated_timer(struct aspeed_gpio *gpio,
|
|
unsigned int offset, unsigned int timer)
|
|
{
|
|
if (WARN(gpio->offset_timer[offset] != 0,
|
|
"Offset %d already allocated timer %d\n",
|
|
offset, gpio->offset_timer[offset]))
|
|
return -EINVAL;
|
|
|
|
if (WARN(gpio->timer_users[timer] == UINT_MAX,
|
|
"Timer user count would overflow\n"))
|
|
return -EPERM;
|
|
|
|
gpio->offset_timer[offset] = timer;
|
|
gpio->timer_users[timer]++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Call under gpio->lock */
|
|
static int unregister_allocated_timer(struct aspeed_gpio *gpio,
|
|
unsigned int offset)
|
|
{
|
|
if (WARN(gpio->offset_timer[offset] == 0,
|
|
"No timer allocated to offset %d\n", offset))
|
|
return -EINVAL;
|
|
|
|
if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
|
|
"No users recorded for timer %d\n",
|
|
gpio->offset_timer[offset]))
|
|
return -EINVAL;
|
|
|
|
gpio->timer_users[gpio->offset_timer[offset]]--;
|
|
gpio->offset_timer[offset] = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Call under gpio->lock */
|
|
static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
|
|
unsigned int offset)
|
|
{
|
|
return gpio->offset_timer[offset] > 0;
|
|
}
|
|
|
|
/* Call under gpio->lock */
|
|
static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
|
|
unsigned int timer)
|
|
{
|
|
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
|
const u32 mask = GPIO_BIT(offset);
|
|
void __iomem *addr;
|
|
u32 val;
|
|
|
|
/* Note: Debounce timer isn't under control of the command
|
|
* source registers, so no need to sync with the coprocessor
|
|
*/
|
|
addr = bank_reg(gpio, bank, reg_debounce_sel1);
|
|
val = ioread32(addr);
|
|
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
|
|
|
|
addr = bank_reg(gpio, bank, reg_debounce_sel2);
|
|
val = ioread32(addr);
|
|
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
|
|
}
|
|
|
|
static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
|
|
unsigned long usecs)
|
|
{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
u32 requested_cycles;
|
|
unsigned long flags;
|
|
int rc;
|
|
int i;
|
|
|
|
if (!gpio->clk)
|
|
return -EINVAL;
|
|
|
|
rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
|
|
if (rc < 0) {
|
|
dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
|
|
usecs, clk_get_rate(gpio->clk), rc);
|
|
return rc;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
|
|
if (timer_allocation_registered(gpio, offset)) {
|
|
rc = unregister_allocated_timer(gpio, offset);
|
|
if (rc < 0)
|
|
goto out;
|
|
}
|
|
|
|
/* Try to find a timer already configured for the debounce period */
|
|
for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
|
|
u32 cycles;
|
|
|
|
cycles = ioread32(gpio->base + debounce_timers[i]);
|
|
if (requested_cycles == cycles)
|
|
break;
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(debounce_timers)) {
|
|
int j;
|
|
|
|
/*
|
|
* As there are no timers configured for the requested debounce
|
|
* period, find an unused timer instead
|
|
*/
|
|
for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
|
|
if (gpio->timer_users[j] == 0)
|
|
break;
|
|
}
|
|
|
|
if (j == ARRAY_SIZE(gpio->timer_users)) {
|
|
dev_warn(chip->parent,
|
|
"Debounce timers exhausted, cannot debounce for period %luus\n",
|
|
usecs);
|
|
|
|
rc = -EPERM;
|
|
|
|
/*
|
|
* We already adjusted the accounting to remove @offset
|
|
* as a user of its previous timer, so also configure
|
|
* the hardware so @offset has timers disabled for
|
|
* consistency.
|
|
*/
|
|
configure_timer(gpio, offset, 0);
|
|
goto out;
|
|
}
|
|
|
|
i = j;
|
|
|
|
iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
|
|
}
|
|
|
|
if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
|
|
rc = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
register_allocated_timer(gpio, offset, i);
|
|
configure_timer(gpio, offset, i);
|
|
|
|
out:
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
|
|
{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
unsigned long flags;
|
|
int rc;
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
|
|
rc = unregister_allocated_timer(gpio, offset);
|
|
if (!rc)
|
|
configure_timer(gpio, offset, 0);
|
|
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int set_debounce(struct gpio_chip *chip, unsigned int offset,
|
|
unsigned long usecs)
|
|
{
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
|
|
if (!have_debounce(gpio, offset))
|
|
return -ENOTSUPP;
|
|
|
|
if (usecs)
|
|
return enable_debounce(chip, offset, usecs);
|
|
|
|
return disable_debounce(chip, offset);
|
|
}
|
|
|
|
static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|
unsigned long config)
|
|
{
|
|
unsigned long param = pinconf_to_config_param(config);
|
|
u32 arg = pinconf_to_config_argument(config);
|
|
|
|
if (param == PIN_CONFIG_INPUT_DEBOUNCE)
|
|
return set_debounce(chip, offset, arg);
|
|
else if (param == PIN_CONFIG_BIAS_DISABLE ||
|
|
param == PIN_CONFIG_BIAS_PULL_DOWN ||
|
|
param == PIN_CONFIG_DRIVE_STRENGTH)
|
|
return pinctrl_gpio_set_config(offset, config);
|
|
else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
|
|
param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
|
|
/* Return -ENOTSUPP to trigger emulation, as per datasheet */
|
|
return -ENOTSUPP;
|
|
else if (param == PIN_CONFIG_PERSIST_STATE)
|
|
return aspeed_gpio_reset_tolerance(chip, offset, arg);
|
|
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
/**
|
|
* aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
|
|
* the coprocessor for shared GPIO banks
|
|
* @ops: The callbacks
|
|
* @data: Pointer passed back to the callbacks
|
|
*/
|
|
int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
|
|
{
|
|
copro_data = data;
|
|
copro_ops = ops;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
|
|
|
|
/**
|
|
* aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
|
|
* bank gets marked and any access from the ARM will
|
|
* result in handshaking via callbacks.
|
|
* @desc: The GPIO to be marked
|
|
* @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
|
|
* @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
|
|
* @bit: If non-NULL, returns the bit number of the GPIO in the registers
|
|
*/
|
|
int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
|
|
u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
|
|
{
|
|
struct gpio_chip *chip = gpiod_to_chip(desc);
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
|
|
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
|
unsigned long flags;
|
|
|
|
if (!gpio->cf_copro_bankmap)
|
|
gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
|
|
if (!gpio->cf_copro_bankmap)
|
|
return -ENOMEM;
|
|
if (offset < 0 || offset > gpio->chip.ngpio)
|
|
return -EINVAL;
|
|
bindex = offset >> 3;
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
|
|
/* Sanity check, this shouldn't happen */
|
|
if (gpio->cf_copro_bankmap[bindex] == 0xff) {
|
|
rc = -EIO;
|
|
goto bail;
|
|
}
|
|
gpio->cf_copro_bankmap[bindex]++;
|
|
|
|
/* Switch command source */
|
|
if (gpio->cf_copro_bankmap[bindex] == 1)
|
|
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
|
|
GPIO_CMDSRC_COLDFIRE);
|
|
|
|
if (vreg_offset)
|
|
*vreg_offset = bank->val_regs;
|
|
if (dreg_offset)
|
|
*dreg_offset = bank->rdata_reg;
|
|
if (bit)
|
|
*bit = GPIO_OFFSET(offset);
|
|
bail:
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
|
|
|
|
/**
|
|
* aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
|
|
* @desc: The GPIO to be marked
|
|
*/
|
|
int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
|
|
{
|
|
struct gpio_chip *chip = gpiod_to_chip(desc);
|
|
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
|
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
|
|
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
|
unsigned long flags;
|
|
|
|
if (!gpio->cf_copro_bankmap)
|
|
return -ENXIO;
|
|
|
|
if (offset < 0 || offset > gpio->chip.ngpio)
|
|
return -EINVAL;
|
|
bindex = offset >> 3;
|
|
|
|
raw_spin_lock_irqsave(&gpio->lock, flags);
|
|
|
|
/* Sanity check, this shouldn't happen */
|
|
if (gpio->cf_copro_bankmap[bindex] == 0) {
|
|
rc = -EIO;
|
|
goto bail;
|
|
}
|
|
gpio->cf_copro_bankmap[bindex]--;
|
|
|
|
/* Switch command source */
|
|
if (gpio->cf_copro_bankmap[bindex] == 0)
|
|
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
|
|
GPIO_CMDSRC_ARM);
|
|
bail:
|
|
raw_spin_unlock_irqrestore(&gpio->lock, flags);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
|
|
|
|
/*
|
|
* Any banks not specified in a struct aspeed_bank_props array are assumed to
|
|
* have the properties:
|
|
*
|
|
* { .input = 0xffffffff, .output = 0xffffffff }
|
|
*/
|
|
|
|
static const struct aspeed_bank_props ast2400_bank_props[] = {
|
|
/* input output */
|
|
{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
|
|
{ 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
|
|
{ },
|
|
};
|
|
|
|
static const struct aspeed_gpio_config ast2400_config =
|
|
/* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
|
|
{ .nr_gpios = 220, .props = ast2400_bank_props, };
|
|
|
|
static const struct aspeed_bank_props ast2500_bank_props[] = {
|
|
/* input output */
|
|
{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
|
|
{ 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
|
|
{ 7, 0x000000ff, 0x000000ff }, /* AC */
|
|
{ },
|
|
};
|
|
|
|
static const struct aspeed_gpio_config ast2500_config =
|
|
/* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
|
|
{ .nr_gpios = 232, .props = ast2500_bank_props, };
|
|
|
|
static const struct aspeed_bank_props ast2600_bank_props[] = {
|
|
/* input output */
|
|
{4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
|
|
{5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
|
|
{6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
|
|
{ },
|
|
};
|
|
|
|
static const struct aspeed_gpio_config ast2600_config =
|
|
/*
|
|
* ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
|
|
* We expect ngpio being set in the device tree and this is a fallback
|
|
* option.
|
|
*/
|
|
{ .nr_gpios = 208, .props = ast2600_bank_props, };
|
|
|
|
static const struct of_device_id aspeed_gpio_of_table[] = {
|
|
{ .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
|
|
{ .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
|
|
{ .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
|
|
|
|
static int __init aspeed_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *gpio_id;
|
|
struct aspeed_gpio *gpio;
|
|
int rc, i, banks, err;
|
|
u32 ngpio;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
if (!gpio)
|
|
return -ENOMEM;
|
|
|
|
gpio->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(gpio->base))
|
|
return PTR_ERR(gpio->base);
|
|
|
|
raw_spin_lock_init(&gpio->lock);
|
|
|
|
gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
|
|
if (!gpio_id)
|
|
return -EINVAL;
|
|
|
|
gpio->clk = of_clk_get(pdev->dev.of_node, 0);
|
|
if (IS_ERR(gpio->clk)) {
|
|
dev_warn(&pdev->dev,
|
|
"Failed to get clock from devicetree, debouncing disabled\n");
|
|
gpio->clk = NULL;
|
|
}
|
|
|
|
gpio->config = gpio_id->data;
|
|
|
|
gpio->chip.parent = &pdev->dev;
|
|
err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
|
|
gpio->chip.ngpio = (u16) ngpio;
|
|
if (err)
|
|
gpio->chip.ngpio = gpio->config->nr_gpios;
|
|
gpio->chip.direction_input = aspeed_gpio_dir_in;
|
|
gpio->chip.direction_output = aspeed_gpio_dir_out;
|
|
gpio->chip.get_direction = aspeed_gpio_get_direction;
|
|
gpio->chip.request = aspeed_gpio_request;
|
|
gpio->chip.free = aspeed_gpio_free;
|
|
gpio->chip.get = aspeed_gpio_get;
|
|
gpio->chip.set = aspeed_gpio_set;
|
|
gpio->chip.set_config = aspeed_gpio_set_config;
|
|
gpio->chip.label = dev_name(&pdev->dev);
|
|
gpio->chip.base = -1;
|
|
|
|
/* Allocate a cache of the output registers */
|
|
banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
|
|
gpio->dcache = devm_kcalloc(&pdev->dev,
|
|
banks, sizeof(u32), GFP_KERNEL);
|
|
if (!gpio->dcache)
|
|
return -ENOMEM;
|
|
|
|
/*
|
|
* Populate it with initial values read from the HW and switch
|
|
* all command sources to the ARM by default
|
|
*/
|
|
for (i = 0; i < banks; i++) {
|
|
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
|
|
void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
|
|
gpio->dcache[i] = ioread32(addr);
|
|
aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
|
|
aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
|
|
aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
|
|
aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
|
|
}
|
|
|
|
/* Optionally set up an irqchip if there is an IRQ */
|
|
rc = platform_get_irq(pdev, 0);
|
|
if (rc > 0) {
|
|
struct gpio_irq_chip *girq;
|
|
|
|
gpio->irq = rc;
|
|
girq = &gpio->chip.irq;
|
|
girq->chip = &gpio->irqc;
|
|
girq->chip->name = dev_name(&pdev->dev);
|
|
girq->chip->irq_ack = aspeed_gpio_irq_ack;
|
|
girq->chip->irq_mask = aspeed_gpio_irq_mask;
|
|
girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
|
|
girq->chip->irq_set_type = aspeed_gpio_set_type;
|
|
girq->parent_handler = aspeed_gpio_irq_handler;
|
|
girq->num_parents = 1;
|
|
girq->parents = devm_kcalloc(&pdev->dev, 1,
|
|
sizeof(*girq->parents),
|
|
GFP_KERNEL);
|
|
if (!girq->parents)
|
|
return -ENOMEM;
|
|
girq->parents[0] = gpio->irq;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_bad_irq;
|
|
girq->init_valid_mask = aspeed_init_irq_valid_mask;
|
|
}
|
|
|
|
gpio->offset_timer =
|
|
devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
|
|
if (!gpio->offset_timer)
|
|
return -ENOMEM;
|
|
|
|
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver aspeed_gpio_driver = {
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.of_match_table = aspeed_gpio_of_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
|
|
|
|
MODULE_DESCRIPTION("Aspeed GPIO Driver");
|
|
MODULE_LICENSE("GPL");
|