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![Neil Armstrong](/assets/img/avatar_default.png)
In order to reduce the kernel Image size on multi-platform distributions, make it possible to build the Amlogic GPIO IRQ controller as a module by switching it to a platform driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Saravana Kannan <saravanak@google.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210902134914.176986-2-narmstrong@baylibre.com
528 lines
14 KiB
C
528 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define NUM_CHANNEL 8
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#define MAX_INPUT_MUX 256
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#define REG_EDGE_POL 0x00
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#define REG_PIN_03_SEL 0x04
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#define REG_PIN_47_SEL 0x08
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#define REG_FILTER_SEL 0x0c
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/* use for A1 like chips */
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#define REG_PIN_A1_SEL 0x04
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/*
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* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
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* bits 24 to 31. Tests on the actual HW show that these bits are
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* stuck at 0. Bits 8 to 15 are responsive and have the expected
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* effect.
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*/
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#define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x))
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#define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x))
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#define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x))
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#define REG_EDGE_POL_MASK(params, x) ( \
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REG_EDGE_POL_EDGE(params, x) | \
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REG_EDGE_POL_LOW(params, x) | \
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REG_BOTH_EDGE(params, x))
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#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
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#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
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struct meson_gpio_irq_controller;
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static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel, unsigned long hwirq);
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static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
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static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel,
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unsigned long hwirq);
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static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
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struct irq_ctl_ops {
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void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
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unsigned int channel, unsigned long hwirq);
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void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
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};
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struct meson_gpio_irq_params {
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unsigned int nr_hwirq;
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bool support_edge_both;
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unsigned int edge_both_offset;
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unsigned int edge_single_offset;
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unsigned int pol_low_offset;
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unsigned int pin_sel_mask;
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struct irq_ctl_ops ops;
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};
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#define INIT_MESON_COMMON(irqs, init, sel) \
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.nr_hwirq = irqs, \
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.ops = { \
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.gpio_irq_init = init, \
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.gpio_irq_sel_pin = sel, \
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},
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#define INIT_MESON8_COMMON_DATA(irqs) \
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INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
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meson8_gpio_irq_sel_pin) \
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.edge_single_offset = 0, \
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.pol_low_offset = 16, \
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.pin_sel_mask = 0xff, \
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#define INIT_MESON_A1_COMMON_DATA(irqs) \
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INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin) \
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.support_edge_both = true, \
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.edge_both_offset = 16, \
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.edge_single_offset = 8, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0x7f, \
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static const struct meson_gpio_irq_params meson8_params = {
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INIT_MESON8_COMMON_DATA(134)
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};
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static const struct meson_gpio_irq_params meson8b_params = {
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INIT_MESON8_COMMON_DATA(119)
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};
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static const struct meson_gpio_irq_params gxbb_params = {
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INIT_MESON8_COMMON_DATA(133)
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};
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static const struct meson_gpio_irq_params gxl_params = {
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INIT_MESON8_COMMON_DATA(110)
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};
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static const struct meson_gpio_irq_params axg_params = {
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INIT_MESON8_COMMON_DATA(100)
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};
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static const struct meson_gpio_irq_params sm1_params = {
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INIT_MESON8_COMMON_DATA(100)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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static const struct meson_gpio_irq_params a1_params = {
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INIT_MESON_A1_COMMON_DATA(62)
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};
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static const struct of_device_id meson_irq_gpio_matches[] = {
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{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
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{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
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{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
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{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
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{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
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{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
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{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
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{ }
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};
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struct meson_gpio_irq_controller {
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const struct meson_gpio_irq_params *params;
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void __iomem *base;
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u32 channel_irqs[NUM_CHANNEL];
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DECLARE_BITMAP(channel_map, NUM_CHANNEL);
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spinlock_t lock;
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};
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static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
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unsigned int reg, u32 mask, u32 val)
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{
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unsigned long flags;
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u32 tmp;
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spin_lock_irqsave(&ctl->lock, flags);
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tmp = readl_relaxed(ctl->base + reg);
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tmp &= ~mask;
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tmp |= val;
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writel_relaxed(tmp, ctl->base + reg);
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spin_unlock_irqrestore(&ctl->lock, flags);
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}
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static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
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{
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}
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static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel, unsigned long hwirq)
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{
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unsigned int reg_offset;
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unsigned int bit_offset;
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reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
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bit_offset = REG_PIN_SEL_SHIFT(channel);
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meson_gpio_irq_update_bits(ctl, reg_offset,
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ctl->params->pin_sel_mask << bit_offset,
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hwirq << bit_offset);
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}
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static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel,
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unsigned long hwirq)
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{
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unsigned int reg_offset;
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unsigned int bit_offset;
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bit_offset = ((channel % 2) == 0) ? 0 : 16;
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reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
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meson_gpio_irq_update_bits(ctl, reg_offset,
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ctl->params->pin_sel_mask << bit_offset,
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hwirq << bit_offset);
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}
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/* For a1 or later chips like a1 there is a switch to enable/disable irq */
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static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
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{
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
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}
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static int
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meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
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unsigned long hwirq,
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u32 **channel_hwirq)
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{
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unsigned long flags;
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unsigned int idx;
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spin_lock_irqsave(&ctl->lock, flags);
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/* Find a free channel */
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idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
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if (idx >= NUM_CHANNEL) {
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spin_unlock_irqrestore(&ctl->lock, flags);
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pr_err("No channel available\n");
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return -ENOSPC;
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}
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/* Mark the channel as used */
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set_bit(idx, ctl->channel_map);
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spin_unlock_irqrestore(&ctl->lock, flags);
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/*
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* Setup the mux of the channel to route the signal of the pad
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* to the appropriate input of the GIC
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*/
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ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
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/*
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* Get the hwirq number assigned to this channel through
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* a pointer the channel_irq table. The added benefit of this
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* method is that we can also retrieve the channel index with
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* it, using the table base.
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*/
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*channel_hwirq = &(ctl->channel_irqs[idx]);
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pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
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hwirq, idx, **channel_hwirq);
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return 0;
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}
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static unsigned int
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meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
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u32 *channel_hwirq)
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{
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return channel_hwirq - ctl->channel_irqs;
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}
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static void
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meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
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u32 *channel_hwirq)
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{
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unsigned int idx;
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idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
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clear_bit(idx, ctl->channel_map);
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}
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static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
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unsigned int type,
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u32 *channel_hwirq)
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{
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u32 val = 0;
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unsigned int idx;
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const struct meson_gpio_irq_params *params;
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params = ctl->params;
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idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
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/*
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* The controller has a filter block to operate in either LEVEL or
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* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
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* EDGE_FALLING support (which the GIC does not support), the filter
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* block is also able to invert the input signal it gets before
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* providing it to the GIC.
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*/
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type &= IRQ_TYPE_SENSE_MASK;
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/*
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* New controller support EDGE_BOTH trigger. This setting takes
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* precedence over the other edge/polarity settings
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*/
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if (type == IRQ_TYPE_EDGE_BOTH) {
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if (!params->support_edge_both)
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return -EINVAL;
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val |= REG_BOTH_EDGE(params, idx);
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} else {
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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val |= REG_EDGE_POL_EDGE(params, idx);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
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val |= REG_EDGE_POL_LOW(params, idx);
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}
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
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REG_EDGE_POL_MASK(params, idx), val);
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return 0;
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}
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static unsigned int meson_gpio_irq_type_output(unsigned int type)
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{
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unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
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type &= ~IRQ_TYPE_SENSE_MASK;
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/*
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* The polarity of the signal provided to the GIC should always
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* be high.
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*/
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if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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type |= IRQ_TYPE_LEVEL_HIGH;
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else
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type |= IRQ_TYPE_EDGE_RISING;
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return type;
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}
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static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct meson_gpio_irq_controller *ctl = data->domain->host_data;
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u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
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int ret;
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ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
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if (ret)
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return ret;
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return irq_chip_set_type_parent(data,
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meson_gpio_irq_type_output(type));
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}
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static struct irq_chip meson_gpio_irq_chip = {
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.name = "meson-gpio-irqchip",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = meson_gpio_irq_set_type,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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return -EINVAL;
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}
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static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
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unsigned int virq,
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u32 hwirq,
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unsigned int type)
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{
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struct irq_fwspec fwspec;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0; /* SPI */
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fwspec.param[1] = hwirq;
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fwspec.param[2] = meson_gpio_irq_type_output(type);
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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}
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static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct meson_gpio_irq_controller *ctl = domain->host_data;
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unsigned long hwirq;
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u32 *channel_hwirq;
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unsigned int type;
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int ret;
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if (WARN_ON(nr_irqs != 1))
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return -EINVAL;
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ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
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if (ret)
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return ret;
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ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
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*channel_hwirq, type);
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if (ret < 0) {
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pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
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meson_gpio_irq_release_channel(ctl, channel_hwirq);
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return ret;
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}
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&meson_gpio_irq_chip, channel_hwirq);
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return 0;
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}
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static void meson_gpio_irq_domain_free(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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struct meson_gpio_irq_controller *ctl = domain->host_data;
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struct irq_data *irq_data;
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u32 *channel_hwirq;
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if (WARN_ON(nr_irqs != 1))
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return;
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irq_domain_free_irqs_parent(domain, virq, 1);
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irq_data = irq_domain_get_irq_data(domain, virq);
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channel_hwirq = irq_data_get_irq_chip_data(irq_data);
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meson_gpio_irq_release_channel(ctl, channel_hwirq);
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}
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static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
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.alloc = meson_gpio_irq_domain_alloc,
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.free = meson_gpio_irq_domain_free,
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.translate = meson_gpio_irq_domain_translate,
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};
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static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl)
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{
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const struct of_device_id *match;
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int ret;
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match = of_match_node(meson_irq_gpio_matches, node);
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if (!match)
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return -ENODEV;
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ctl->params = match->data;
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ret = of_property_read_variable_u32_array(node,
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"amlogic,channel-interrupts",
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ctl->channel_irqs,
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NUM_CHANNEL,
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NUM_CHANNEL);
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if (ret < 0) {
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pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
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return ret;
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}
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ctl->params->ops.gpio_irq_init(ctl);
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return 0;
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}
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static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *domain, *parent_domain;
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struct meson_gpio_irq_controller *ctl;
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int ret;
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if (!parent) {
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pr_err("missing parent interrupt node\n");
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("unable to obtain parent domain\n");
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return -ENXIO;
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}
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ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
|
|
if (!ctl)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&ctl->lock);
|
|
|
|
ctl->base = of_iomap(node, 0);
|
|
if (!ctl->base) {
|
|
ret = -ENOMEM;
|
|
goto free_ctl;
|
|
}
|
|
|
|
ret = meson_gpio_irq_parse_dt(node, ctl);
|
|
if (ret)
|
|
goto free_channel_irqs;
|
|
|
|
domain = irq_domain_create_hierarchy(parent_domain, 0,
|
|
ctl->params->nr_hwirq,
|
|
of_node_to_fwnode(node),
|
|
&meson_gpio_irq_domain_ops,
|
|
ctl);
|
|
if (!domain) {
|
|
pr_err("failed to add domain\n");
|
|
ret = -ENODEV;
|
|
goto free_channel_irqs;
|
|
}
|
|
|
|
pr_info("%d to %d gpio interrupt mux initialized\n",
|
|
ctl->params->nr_hwirq, NUM_CHANNEL);
|
|
|
|
return 0;
|
|
|
|
free_channel_irqs:
|
|
iounmap(ctl->base);
|
|
free_ctl:
|
|
kfree(ctl);
|
|
|
|
return ret;
|
|
}
|
|
|
|
IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc)
|
|
IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
|
|
IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc)
|
|
|
|
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:meson-gpio-intc");
|