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![Zhang Qilong](/assets/img/avatar_default.png)
pm_runtime_get_sync will increment pm usage counter even it
failed. Forgetting to pm_runtime_put_noidle will result in
reference leak in mxs_spi_probe, so we should fix it.
Fixes: b7969caf41
("spi: mxs: implement runtime pm")
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20201106012421.95420-1-zhangqilong3@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
676 lines
16 KiB
C
676 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Freescale MXS SPI master driver
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//
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// Copyright 2012 DENX Software Engineering, GmbH.
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// Copyright 2012 Freescale Semiconductor, Inc.
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// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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//
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// Rework and transition to new API by:
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// Marek Vasut <marex@denx.de>
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//
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// Based on previous attempt by:
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// Fabio Estevam <fabio.estevam@freescale.com>
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//
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// Based on code from U-Boot bootloader by:
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// Marek Vasut <marex@denx.de>
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//
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// Based on spi-stmp.c, which is:
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// Author: Dmitry Pervushin <dimka@embeddedalley.com>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/highmem.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/module.h>
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#include <linux/stmp_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/mxs-spi.h>
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#include <trace/events/spi.h>
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#define DRIVER_NAME "mxs-spi"
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/* Use 10S timeout for very long transfers, it should suffice. */
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#define SSP_TIMEOUT 10000
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#define SG_MAXLEN 0xff00
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/*
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* Flags for txrx functions. More efficient that using an argument register for
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* each one.
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*/
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#define TXRX_WRITE (1<<0) /* This is a write */
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#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
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struct mxs_spi {
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struct mxs_ssp ssp;
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struct completion c;
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unsigned int sck; /* Rate requested (vs actual) */
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};
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static int mxs_spi_setup_transfer(struct spi_device *dev,
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const struct spi_transfer *t)
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{
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struct mxs_spi *spi = spi_master_get_devdata(dev->master);
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struct mxs_ssp *ssp = &spi->ssp;
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const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
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if (hz == 0) {
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dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
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return -EINVAL;
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}
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if (hz != spi->sck) {
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mxs_ssp_set_clk_rate(ssp, hz);
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/*
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* Save requested rate, hz, rather than the actual rate,
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* ssp->clk_rate. Otherwise we would set the rate every transfer
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* when the actual rate is not quite the same as requested rate.
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*/
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spi->sck = hz;
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/*
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* Perhaps we should return an error if the actual clock is
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* nowhere close to what was requested?
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*/
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}
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writel(BM_SSP_CTRL0_LOCK_CS,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
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BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
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((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
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((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
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ssp->base + HW_SSP_CTRL1(ssp));
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writel(0x0, ssp->base + HW_SSP_CMD0);
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writel(0x0, ssp->base + HW_SSP_CMD1);
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return 0;
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}
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static u32 mxs_spi_cs_to_reg(unsigned cs)
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{
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u32 select = 0;
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/*
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* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
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*
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* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
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* in HW_SSP_CTRL0 register do have multiple usage, please refer to
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* the datasheet for further details. In SPI mode, they are used to
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* toggle the chip-select lines (nCS pins).
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*/
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if (cs & 1)
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select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
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if (cs & 2)
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select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
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return select;
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}
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static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
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{
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const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
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struct mxs_ssp *ssp = &spi->ssp;
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u32 reg;
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do {
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reg = readl_relaxed(ssp->base + offset);
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if (!set)
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reg = ~reg;
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reg &= mask;
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if (reg == mask)
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return 0;
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} while (time_before(jiffies, timeout));
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return -ETIMEDOUT;
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}
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static void mxs_ssp_dma_irq_callback(void *param)
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{
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struct mxs_spi *spi = param;
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complete(&spi->c);
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}
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static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
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{
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struct mxs_ssp *ssp = dev_id;
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dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
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__func__, __LINE__,
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readl(ssp->base + HW_SSP_CTRL1(ssp)),
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readl(ssp->base + HW_SSP_STATUS(ssp)));
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return IRQ_HANDLED;
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}
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static int mxs_spi_txrx_dma(struct mxs_spi *spi,
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unsigned char *buf, int len,
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unsigned int flags)
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{
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struct mxs_ssp *ssp = &spi->ssp;
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struct dma_async_tx_descriptor *desc = NULL;
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const bool vmalloced_buf = is_vmalloc_addr(buf);
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const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
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const int sgs = DIV_ROUND_UP(len, desc_len);
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int sg_count;
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int min, ret;
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u32 ctrl0;
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struct page *vm_page;
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struct {
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u32 pio[4];
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struct scatterlist sg;
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} *dma_xfer;
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if (!len)
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return -EINVAL;
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dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
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if (!dma_xfer)
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return -ENOMEM;
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reinit_completion(&spi->c);
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/* Chip select was already programmed into CTRL0 */
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ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
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ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
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BM_SSP_CTRL0_READ);
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ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
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if (!(flags & TXRX_WRITE))
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ctrl0 |= BM_SSP_CTRL0_READ;
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/* Queue the DMA data transfer. */
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for (sg_count = 0; sg_count < sgs; sg_count++) {
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/* Prepare the transfer descriptor. */
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min = min(len, desc_len);
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/*
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* De-assert CS on last segment if flag is set (i.e., no more
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* transfers will follow)
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*/
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if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
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ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
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if (ssp->devid == IMX23_SSP) {
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ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
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ctrl0 |= min;
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}
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dma_xfer[sg_count].pio[0] = ctrl0;
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dma_xfer[sg_count].pio[3] = min;
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if (vmalloced_buf) {
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vm_page = vmalloc_to_page(buf);
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if (!vm_page) {
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ret = -ENOMEM;
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goto err_vmalloc;
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}
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sg_init_table(&dma_xfer[sg_count].sg, 1);
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sg_set_page(&dma_xfer[sg_count].sg, vm_page,
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min, offset_in_page(buf));
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} else {
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sg_init_one(&dma_xfer[sg_count].sg, buf, min);
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}
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ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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len -= min;
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buf += min;
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/* Queue the PIO register write transfer. */
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desc = dmaengine_prep_slave_sg(ssp->dmach,
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(struct scatterlist *)dma_xfer[sg_count].pio,
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(ssp->devid == IMX23_SSP) ? 1 : 4,
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DMA_TRANS_NONE,
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sg_count ? DMA_PREP_INTERRUPT : 0);
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if (!desc) {
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dev_err(ssp->dev,
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"Failed to get PIO reg. write descriptor.\n");
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ret = -EINVAL;
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goto err_mapped;
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}
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desc = dmaengine_prep_slave_sg(ssp->dmach,
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&dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(ssp->dev,
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"Failed to get DMA data write descriptor.\n");
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ret = -EINVAL;
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goto err_mapped;
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}
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}
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/*
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* The last descriptor must have this callback,
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* to finish the DMA transaction.
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*/
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desc->callback = mxs_ssp_dma_irq_callback;
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desc->callback_param = spi;
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/* Start the transfer. */
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dmaengine_submit(desc);
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dma_async_issue_pending(ssp->dmach);
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if (!wait_for_completion_timeout(&spi->c,
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msecs_to_jiffies(SSP_TIMEOUT))) {
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dev_err(ssp->dev, "DMA transfer timeout\n");
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ret = -ETIMEDOUT;
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dmaengine_terminate_all(ssp->dmach);
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goto err_vmalloc;
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}
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ret = 0;
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err_vmalloc:
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while (--sg_count >= 0) {
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err_mapped:
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dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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}
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kfree(dma_xfer);
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return ret;
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}
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static int mxs_spi_txrx_pio(struct mxs_spi *spi,
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unsigned char *buf, int len,
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unsigned int flags)
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{
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struct mxs_ssp *ssp = &spi->ssp;
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writel(BM_SSP_CTRL0_IGNORE_CRC,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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while (len--) {
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if (len == 0 && (flags & TXRX_DEASSERT_CS))
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writel(BM_SSP_CTRL0_IGNORE_CRC,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (ssp->devid == IMX23_SSP) {
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writel(BM_SSP_CTRL0_XFER_COUNT,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(1,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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} else {
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writel(1, ssp->base + HW_SSP_XFER_SIZE);
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}
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if (flags & TXRX_WRITE)
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writel(BM_SSP_CTRL0_READ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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else
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writel(BM_SSP_CTRL0_READ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BM_SSP_CTRL0_RUN,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
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return -ETIMEDOUT;
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if (flags & TXRX_WRITE)
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writel(*buf, ssp->base + HW_SSP_DATA(ssp));
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writel(BM_SSP_CTRL0_DATA_XFER,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (!(flags & TXRX_WRITE)) {
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if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
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BM_SSP_STATUS_FIFO_EMPTY, 0))
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return -ETIMEDOUT;
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*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
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}
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if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
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return -ETIMEDOUT;
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buf++;
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}
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if (len <= 0)
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return 0;
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return -ETIMEDOUT;
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}
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static int mxs_spi_transfer_one(struct spi_master *master,
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struct spi_message *m)
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{
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struct mxs_spi *spi = spi_master_get_devdata(master);
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struct mxs_ssp *ssp = &spi->ssp;
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struct spi_transfer *t;
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unsigned int flag;
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int status = 0;
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/* Program CS register bits here, it will be used for all transfers. */
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writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(mxs_spi_cs_to_reg(m->spi->chip_select),
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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trace_spi_transfer_start(m, t);
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status = mxs_spi_setup_transfer(m->spi, t);
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if (status)
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break;
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/* De-assert on last transfer, inverted by cs_change flag */
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flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
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TXRX_DEASSERT_CS : 0;
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/*
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* Small blocks can be transfered via PIO.
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* Measured by empiric means:
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*
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* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
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*
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* DMA only: 2.164808 seconds, 473.0KB/s
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* Combined: 1.676276 seconds, 610.9KB/s
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*/
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if (t->len < 32) {
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writel(BM_SSP_CTRL1_DMA_ENABLE,
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ssp->base + HW_SSP_CTRL1(ssp) +
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STMP_OFFSET_REG_CLR);
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if (t->tx_buf)
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status = mxs_spi_txrx_pio(spi,
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(void *)t->tx_buf,
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t->len, flag | TXRX_WRITE);
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if (t->rx_buf)
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status = mxs_spi_txrx_pio(spi,
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t->rx_buf, t->len,
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flag);
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} else {
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writel(BM_SSP_CTRL1_DMA_ENABLE,
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ssp->base + HW_SSP_CTRL1(ssp) +
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STMP_OFFSET_REG_SET);
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if (t->tx_buf)
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status = mxs_spi_txrx_dma(spi,
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(void *)t->tx_buf, t->len,
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flag | TXRX_WRITE);
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if (t->rx_buf)
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status = mxs_spi_txrx_dma(spi,
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t->rx_buf, t->len,
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flag);
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}
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trace_spi_transfer_stop(m, t);
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if (status) {
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stmp_reset_block(ssp->base);
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break;
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}
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m->actual_length += t->len;
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}
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m->status = status;
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spi_finalize_current_message(master);
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return status;
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}
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static int mxs_spi_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mxs_spi *spi = spi_master_get_devdata(master);
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struct mxs_ssp *ssp = &spi->ssp;
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int ret;
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clk_disable_unprepare(ssp->clk);
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ret = pinctrl_pm_select_idle_state(dev);
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if (ret) {
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int ret2 = clk_prepare_enable(ssp->clk);
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if (ret2)
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dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
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ret, ret2);
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}
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return ret;
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}
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static int mxs_spi_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mxs_spi *spi = spi_master_get_devdata(master);
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struct mxs_ssp *ssp = &spi->ssp;
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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ret = clk_prepare_enable(ssp->clk);
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if (ret)
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pinctrl_pm_select_idle_state(dev);
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return ret;
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}
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static int __maybe_unused mxs_spi_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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int ret;
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ret = spi_master_suspend(master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!pm_runtime_suspended(dev))
|
|
return mxs_spi_runtime_suspend(dev);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mxs_spi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
if (!pm_runtime_suspended(dev))
|
|
ret = mxs_spi_runtime_resume(dev);
|
|
else
|
|
ret = 0;
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = spi_master_resume(master);
|
|
if (ret < 0 && !pm_runtime_suspended(dev))
|
|
mxs_spi_runtime_suspend(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops mxs_spi_pm = {
|
|
SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
|
|
mxs_spi_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
|
|
};
|
|
|
|
static const struct of_device_id mxs_spi_dt_ids[] = {
|
|
{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
|
|
{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
|
|
|
|
static int mxs_spi_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id =
|
|
of_match_device(mxs_spi_dt_ids, &pdev->dev);
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct spi_master *master;
|
|
struct mxs_spi *spi;
|
|
struct mxs_ssp *ssp;
|
|
struct clk *clk;
|
|
void __iomem *base;
|
|
int devid, clk_freq;
|
|
int ret = 0, irq_err;
|
|
|
|
/*
|
|
* Default clock speed for the SPI core. 160MHz seems to
|
|
* work reasonably well with most SPI flashes, so use this
|
|
* as a default. Override with "clock-frequency" DT prop.
|
|
*/
|
|
const int clk_freq_default = 160000000;
|
|
|
|
irq_err = platform_get_irq(pdev, 0);
|
|
if (irq_err < 0)
|
|
return irq_err;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
devid = (enum mxs_ssp_id) of_id->data;
|
|
ret = of_property_read_u32(np, "clock-frequency",
|
|
&clk_freq);
|
|
if (ret)
|
|
clk_freq = clk_freq_default;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*spi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
master->transfer_one_message = mxs_spi_transfer_one;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
|
master->num_chipselect = 3;
|
|
master->dev.of_node = np;
|
|
master->flags = SPI_MASTER_HALF_DUPLEX;
|
|
master->auto_runtime_pm = true;
|
|
|
|
spi = spi_master_get_devdata(master);
|
|
ssp = &spi->ssp;
|
|
ssp->dev = &pdev->dev;
|
|
ssp->clk = clk;
|
|
ssp->base = base;
|
|
ssp->devid = devid;
|
|
|
|
init_completion(&spi->c);
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
|
|
dev_name(&pdev->dev), ssp);
|
|
if (ret)
|
|
goto out_master_free;
|
|
|
|
ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
|
|
if (IS_ERR(ssp->dmach)) {
|
|
dev_err(ssp->dev, "Failed to request DMA\n");
|
|
ret = PTR_ERR(ssp->dmach);
|
|
goto out_master_free;
|
|
}
|
|
|
|
pm_runtime_enable(ssp->dev);
|
|
if (!pm_runtime_enabled(ssp->dev)) {
|
|
ret = mxs_spi_runtime_resume(ssp->dev);
|
|
if (ret < 0) {
|
|
dev_err(ssp->dev, "runtime resume failed\n");
|
|
goto out_dma_release;
|
|
}
|
|
}
|
|
|
|
ret = pm_runtime_get_sync(ssp->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(ssp->dev);
|
|
dev_err(ssp->dev, "runtime_get_sync failed\n");
|
|
goto out_pm_runtime_disable;
|
|
}
|
|
|
|
clk_set_rate(ssp->clk, clk_freq);
|
|
|
|
ret = stmp_reset_block(ssp->base);
|
|
if (ret)
|
|
goto out_pm_runtime_put;
|
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
|
|
goto out_pm_runtime_put;
|
|
}
|
|
|
|
pm_runtime_put(ssp->dev);
|
|
|
|
return 0;
|
|
|
|
out_pm_runtime_put:
|
|
pm_runtime_put(ssp->dev);
|
|
out_pm_runtime_disable:
|
|
pm_runtime_disable(ssp->dev);
|
|
out_dma_release:
|
|
dma_release_channel(ssp->dmach);
|
|
out_master_free:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int mxs_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct mxs_spi *spi;
|
|
struct mxs_ssp *ssp;
|
|
|
|
master = platform_get_drvdata(pdev);
|
|
spi = spi_master_get_devdata(master);
|
|
ssp = &spi->ssp;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
mxs_spi_runtime_suspend(&pdev->dev);
|
|
|
|
dma_release_channel(ssp->dmach);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mxs_spi_driver = {
|
|
.probe = mxs_spi_probe,
|
|
.remove = mxs_spi_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = mxs_spi_dt_ids,
|
|
.pm = &mxs_spi_pm,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mxs_spi_driver);
|
|
|
|
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
|
MODULE_DESCRIPTION("MXS SPI master driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:mxs-spi");
|