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a96cbb146a
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
185 lines
7.2 KiB
C
185 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "clk-mux.h"
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#include <dt-bindings/clock/mt7986-clk.h>
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#include <linux/clk.h>
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static DEFINE_SPINLOCK(mt7986_clk_lock);
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static const struct mtk_fixed_factor infra_divs[] = {
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FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
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};
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static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
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"uart_sel" };
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static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
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"spi_sel" };
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static const char *const infra_pwm_bsel_parents[] __initconst = {
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"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
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};
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static const char *const infra_pcie_parents[] __initconst = {
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"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
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};
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static const struct mtk_mux infra_muxes[] = {
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/* MODULE_CLK_SEL_0 */
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
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infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
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infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
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infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
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2, -1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
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infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
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2, -1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
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infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
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2, -1, -1, -1),
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/* MODULE_CLK_SEL_1 */
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
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infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
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-1, -1, -1),
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};
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static const struct mtk_gate_regs infra0_cg_regs = {
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.set_ofs = 0x40,
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.clr_ofs = 0x44,
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.sta_ofs = 0x48,
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};
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static const struct mtk_gate_regs infra1_cg_regs = {
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.set_ofs = 0x50,
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.clr_ofs = 0x54,
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.sta_ofs = 0x58,
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};
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static const struct mtk_gate_regs infra2_cg_regs = {
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.set_ofs = 0x60,
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.clr_ofs = 0x64,
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.sta_ofs = 0x68,
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};
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#define GATE_INFRA0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_INFRA1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_INFRA2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate infra_clks[] = {
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/* INFRA0 */
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GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
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GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
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GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
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GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
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GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
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GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
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GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
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GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
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GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
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GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
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GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
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GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
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GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
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14),
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GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
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GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
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GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
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GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
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GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
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/* INFRA1 */
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GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
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GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
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GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
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GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
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GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
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GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
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GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
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GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
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10),
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GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
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GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
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GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
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13),
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GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
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14),
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GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
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GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
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GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
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17),
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GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
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18),
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GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
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19),
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GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
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GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
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GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
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/* INFRA2 */
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GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
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GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
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1),
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GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
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GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
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GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
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GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
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13),
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GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
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GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
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};
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static const struct mtk_clk_desc infra_desc = {
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.clks = infra_clks,
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.num_clks = ARRAY_SIZE(infra_clks),
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.factor_clks = infra_divs,
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.num_factor_clks = ARRAY_SIZE(infra_divs),
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.mux_clks = infra_muxes,
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.num_mux_clks = ARRAY_SIZE(infra_muxes),
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.clk_lock = &mt7986_clk_lock,
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};
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static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
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{ .compatible = "mediatek,mt7986-infracfg", .data = &infra_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_infracfg);
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static struct platform_driver clk_mt7986_infracfg_drv = {
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.driver = {
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.name = "clk-mt7986-infracfg",
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.of_match_table = of_match_clk_mt7986_infracfg,
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},
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.probe = mtk_clk_simple_probe,
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.remove_new = mtk_clk_simple_remove,
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};
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module_platform_driver(clk_mt7986_infracfg_drv);
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MODULE_DESCRIPTION("MediaTek MT7986 infracfg clocks driver");
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MODULE_LICENSE("GPL");
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