Liu Ying 9a8406ba1a phy: dphy: Correct clk_pre parameter ... The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE parameter's unit is Unit Interval(UI) and the minimum value is 8. Also, kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy mentions that it should be in UI. However, the dphy core driver wrongly sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds. So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE parameter's minimum value according to the D-PHY specification. I'm assuming that all impacted custom drivers shall program values in TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY specification mentions that the frequency of TxByteClkHS is exactly 1/8 the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant custom driver code is changed to program those values as DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then. Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, as I don't have the hardwares. Fixes: 2ed869990e ("phy: Add MIPI D-PHY configuration options") Tested-by: Liu Ying <victor.liu@nxp.com> # RM67191 DSI panel on i.MX8mq EVK Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Guido Günther <agx@sigxcpu.org> # Librem 5 (imx8mq) with it's rather picky panel Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20220124024007.1465018-1-victor.liu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-02-02 10:33:04 +05:30
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allwinner
amlogic	phy: dphy: Correct clk_pre parameter	2022-02-02 10:33:04 +05:30
broadcom	phy: broadcom: Kconfig: Fix PHY_BRCM_USB config option	2022-01-23 19:33:28 +05:30
cadence	phy: cadence: Sierra: fix error handling bugs in probe()	2022-01-24 09:35:31 +05:30
freescale
hisilicon
ingenic
intel
lantiq
marvell
mediatek	phy: phy-mtk-tphy: Fix duplicated argument in phy-mtk-tphy	2022-01-27 12:14:34 +05:30
microchip
motorola
mscc
qualcomm
ralink
renesas
rockchip	phy: dphy: Correct clk_pre parameter	2022-02-02 10:33:04 +05:30
samsung
socionext
st	phy: stm32: fix a refcount leak in stm32_usbphyc_pll_enable()	2022-01-27 11:04:40 +05:30
tegra
ti	phy: ti: Fix missing sentinel for clk_div_table	2022-01-24 09:33:33 +05:30
xilinx	phy: xilinx: zynqmp: Fix bus width setting for SGMII	2022-01-27 10:55:26 +05:30
Kconfig
Makefile
phy-can-transceiver.c
phy-core-mipi-dphy.c	phy: dphy: Correct clk_pre parameter	2022-02-02 10:33:04 +05:30
phy-core.c
phy-lgm-usb.c
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c