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![Paul Gerber](/assets/img/avatar_default.png)
The i.MX 8MP has a ADC_PD bit in the TMU_TER register that controls the
operating mode of the ADC:
* 0 means normal operating mode
* 1 means power down mode
When enabling/disabling the TMU, the ADC operating mode must be set
accordingly.
i.MX 8M Mini & Nano are lacking this bit.
Signed-off-by: Paul Gerber <Paul.Gerber@tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Fixes: 2b8f1f0337
("thermal: imx8mm: Add i.MX8MP support")
Link: https://lore.kernel.org/r/20211122114225.196280-1-alexander.stein@ew.tq-group.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
241 lines
5.4 KiB
C
241 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020 NXP.
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*
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* Author: Anson Huang <Anson.Huang@nxp.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/thermal.h>
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#include "thermal_core.h"
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#define TER 0x0 /* TMU enable */
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#define TPS 0x4
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#define TRITSR 0x20 /* TMU immediate temp */
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#define TER_ADC_PD BIT(30)
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#define TER_EN BIT(31)
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#define TRITSR_TEMP0_VAL_MASK 0xff
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#define TRITSR_TEMP1_VAL_MASK 0xff0000
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#define PROBE_SEL_ALL GENMASK(31, 30)
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#define probe_status_offset(x) (30 + x)
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#define SIGN_BIT BIT(7)
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#define TEMP_VAL_MASK GENMASK(6, 0)
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#define VER1_TEMP_LOW_LIMIT 10000
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#define VER2_TEMP_LOW_LIMIT -40000
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#define VER2_TEMP_HIGH_LIMIT 125000
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#define TMU_VER1 0x1
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#define TMU_VER2 0x2
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struct thermal_soc_data {
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u32 num_sensors;
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u32 version;
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int (*get_temp)(void *, int *);
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};
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struct tmu_sensor {
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struct imx8mm_tmu *priv;
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u32 hw_id;
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struct thermal_zone_device *tzd;
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};
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struct imx8mm_tmu {
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void __iomem *base;
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struct clk *clk;
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const struct thermal_soc_data *socdata;
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struct tmu_sensor sensors[];
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};
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static int imx8mm_tmu_get_temp(void *data, int *temp)
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{
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struct tmu_sensor *sensor = data;
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struct imx8mm_tmu *tmu = sensor->priv;
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u32 val;
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val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;
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*temp = val * 1000;
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if (*temp < VER1_TEMP_LOW_LIMIT)
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return -EAGAIN;
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return 0;
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}
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static int imx8mp_tmu_get_temp(void *data, int *temp)
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{
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struct tmu_sensor *sensor = data;
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struct imx8mm_tmu *tmu = sensor->priv;
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unsigned long val;
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bool ready;
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val = readl_relaxed(tmu->base + TRITSR);
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ready = test_bit(probe_status_offset(sensor->hw_id), &val);
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if (!ready)
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return -EAGAIN;
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val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) :
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FIELD_GET(TRITSR_TEMP0_VAL_MASK, val);
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if (val & SIGN_BIT) /* negative */
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val = (~(val & TEMP_VAL_MASK) + 1);
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*temp = val * 1000;
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if (*temp < VER2_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
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return -EAGAIN;
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return 0;
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}
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static int tmu_get_temp(void *data, int *temp)
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{
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struct tmu_sensor *sensor = data;
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struct imx8mm_tmu *tmu = sensor->priv;
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return tmu->socdata->get_temp(data, temp);
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}
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static struct thermal_zone_of_device_ops tmu_tz_ops = {
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.get_temp = tmu_get_temp,
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};
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static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
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{
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u32 val;
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val = readl_relaxed(tmu->base + TER);
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val = enable ? (val | TER_EN) : (val & ~TER_EN);
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if (tmu->socdata->version == TMU_VER2)
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val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD);
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writel_relaxed(val, tmu->base + TER);
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}
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static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
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{
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u32 val;
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val = readl_relaxed(tmu->base + TPS);
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val |= PROBE_SEL_ALL;
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writel_relaxed(val, tmu->base + TPS);
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}
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static int imx8mm_tmu_probe(struct platform_device *pdev)
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{
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const struct thermal_soc_data *data;
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struct imx8mm_tmu *tmu;
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int ret;
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int i;
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data = of_device_get_match_data(&pdev->dev);
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tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,
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data->num_sensors), GFP_KERNEL);
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if (!tmu)
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return -ENOMEM;
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tmu->socdata = data;
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tmu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(tmu->base))
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return PTR_ERR(tmu->base);
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tmu->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(tmu->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),
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"failed to get tmu clock\n");
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ret = clk_prepare_enable(tmu->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);
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return ret;
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}
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/* disable the monitor during initialization */
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imx8mm_tmu_enable(tmu, false);
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for (i = 0; i < data->num_sensors; i++) {
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tmu->sensors[i].priv = tmu;
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tmu->sensors[i].tzd =
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devm_thermal_zone_of_sensor_register(&pdev->dev, i,
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&tmu->sensors[i],
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&tmu_tz_ops);
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if (IS_ERR(tmu->sensors[i].tzd)) {
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ret = PTR_ERR(tmu->sensors[i].tzd);
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dev_err(&pdev->dev,
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"failed to register thermal zone sensor[%d]: %d\n",
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i, ret);
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goto disable_clk;
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}
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tmu->sensors[i].hw_id = i;
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}
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platform_set_drvdata(pdev, tmu);
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/* enable all the probes for V2 TMU */
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if (tmu->socdata->version == TMU_VER2)
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imx8mm_tmu_probe_sel_all(tmu);
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/* enable the monitor */
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imx8mm_tmu_enable(tmu, true);
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return 0;
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disable_clk:
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clk_disable_unprepare(tmu->clk);
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return ret;
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}
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static int imx8mm_tmu_remove(struct platform_device *pdev)
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{
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struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);
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/* disable TMU */
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imx8mm_tmu_enable(tmu, false);
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clk_disable_unprepare(tmu->clk);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct thermal_soc_data imx8mm_tmu_data = {
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.num_sensors = 1,
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.version = TMU_VER1,
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.get_temp = imx8mm_tmu_get_temp,
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};
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static struct thermal_soc_data imx8mp_tmu_data = {
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.num_sensors = 2,
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.version = TMU_VER2,
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.get_temp = imx8mp_tmu_get_temp,
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};
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static const struct of_device_id imx8mm_tmu_table[] = {
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{ .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
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{ .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx8mm_tmu_table);
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static struct platform_driver imx8mm_tmu = {
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.driver = {
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.name = "i.mx8mm_thermal",
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.of_match_table = imx8mm_tmu_table,
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},
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.probe = imx8mm_tmu_probe,
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.remove = imx8mm_tmu_remove,
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};
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module_platform_driver(imx8mm_tmu);
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MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
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MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver");
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MODULE_LICENSE("GPL v2");
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