mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 08:02:30 +00:00
d22066c1af
TSENS IP v2.3 onwards adds support for a watchdog to detect if the TSENS HW FSM is stuck. Add support to detect and restart the FSM in the driver. The watchdog is configured by the bootloader, we just enable the watchdog bark as a debug feature in the kernel. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/a314747664a065db592ad77da7beae68128a5b6e.1584015867.git.amit.kucheria@linaro.org
110 lines
4 KiB
C
110 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
|
* Copyright (c) 2018, Linaro Limited
|
|
*/
|
|
|
|
#include <linux/bitops.h>
|
|
#include <linux/regmap.h>
|
|
#include "tsens.h"
|
|
|
|
/* ----- SROT ------ */
|
|
#define SROT_HW_VER_OFF 0x0000
|
|
#define SROT_CTRL_OFF 0x0004
|
|
|
|
/* ----- TM ------ */
|
|
#define TM_INT_EN_OFF 0x0004
|
|
#define TM_UPPER_LOWER_INT_STATUS_OFF 0x0008
|
|
#define TM_UPPER_LOWER_INT_CLEAR_OFF 0x000c
|
|
#define TM_UPPER_LOWER_INT_MASK_OFF 0x0010
|
|
#define TM_CRITICAL_INT_STATUS_OFF 0x0014
|
|
#define TM_CRITICAL_INT_CLEAR_OFF 0x0018
|
|
#define TM_CRITICAL_INT_MASK_OFF 0x001c
|
|
#define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
|
|
#define TM_Sn_CRITICAL_THRESHOLD_OFF 0x0060
|
|
#define TM_Sn_STATUS_OFF 0x00a0
|
|
#define TM_TRDY_OFF 0x00e4
|
|
#define TM_WDOG_LOG_OFF 0x013c
|
|
|
|
/* v2.x: 8996, 8998, sdm845 */
|
|
|
|
static struct tsens_features tsens_v2_feat = {
|
|
.ver_major = VER_2_X,
|
|
.crit_int = 1,
|
|
.adc = 0,
|
|
.srot_split = 1,
|
|
.max_sensors = 16,
|
|
};
|
|
|
|
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
|
/* ----- SROT ------ */
|
|
/* VERSION */
|
|
[VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
|
|
[VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
|
|
[VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
|
|
/* CTRL_OFF */
|
|
[TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
|
|
[TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
|
|
|
|
/* ----- TM ------ */
|
|
/* INTERRUPT ENABLE */
|
|
/* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */
|
|
[INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2),
|
|
|
|
/* TEMPERATURE THRESHOLDS */
|
|
REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11),
|
|
REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23),
|
|
REG_FIELD_FOR_EACH_SENSOR16(CRIT_THRESH, TM_Sn_CRITICAL_THRESHOLD_OFF, 0, 11),
|
|
|
|
/* INTERRUPTS [CLEAR/STATUS/MASK] */
|
|
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
|
|
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
|
|
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
|
|
REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
|
|
REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
|
|
REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
|
|
REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_STATUS, TM_CRITICAL_INT_STATUS_OFF),
|
|
REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_CLEAR, TM_CRITICAL_INT_CLEAR_OFF),
|
|
REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_MASK, TM_CRITICAL_INT_MASK_OFF),
|
|
|
|
/* WATCHDOG on v2.3 or later */
|
|
[WDOG_BARK_STATUS] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 31, 31),
|
|
[WDOG_BARK_CLEAR] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF, 31, 31),
|
|
[WDOG_BARK_MASK] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF, 31, 31),
|
|
[CC_MON_STATUS] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 30, 30),
|
|
[CC_MON_CLEAR] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF, 30, 30),
|
|
[CC_MON_MASK] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF, 30, 30),
|
|
[WDOG_BARK_COUNT] = REG_FIELD(TM_WDOG_LOG_OFF, 0, 7),
|
|
|
|
/* Sn_STATUS */
|
|
REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11),
|
|
REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21),
|
|
/* xxx_STATUS bits: 1 == threshold violated */
|
|
REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16),
|
|
REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17),
|
|
REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18),
|
|
REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS, TM_Sn_STATUS_OFF, 19, 19),
|
|
REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS, TM_Sn_STATUS_OFF, 20, 20),
|
|
|
|
/* TRDY: 1=ready, 0=in progress */
|
|
[TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
|
|
};
|
|
|
|
static const struct tsens_ops ops_generic_v2 = {
|
|
.init = init_common,
|
|
.get_temp = get_temp_tsens_valid,
|
|
};
|
|
|
|
struct tsens_plat_data data_tsens_v2 = {
|
|
.ops = &ops_generic_v2,
|
|
.feat = &tsens_v2_feat,
|
|
.fields = tsens_v2_regfields,
|
|
};
|
|
|
|
/* Kept around for backward compatibility with old msm8996.dtsi */
|
|
struct tsens_plat_data data_8996 = {
|
|
.num_sensors = 13,
|
|
.ops = &ops_generic_v2,
|
|
.feat = &tsens_v2_feat,
|
|
.fields = tsens_v2_regfields,
|
|
};
|