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57b971907e
The Camera Subsystem clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Add clock ids for camera clocks which are required to bring the camera subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1602873815-1677-4-git-send-email-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
121 lines
3.8 KiB
C
121 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H
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/* CAM_CC clocks */
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#define CAM_CC_PLL2_OUT_EARLY 0
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#define CAM_CC_PLL0 1
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#define CAM_CC_PLL1 2
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#define CAM_CC_PLL2 3
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#define CAM_CC_PLL2_OUT_AUX 4
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#define CAM_CC_PLL3 5
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#define CAM_CC_CAMNOC_AXI_CLK 6
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#define CAM_CC_CCI_0_CLK 7
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#define CAM_CC_CCI_0_CLK_SRC 8
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#define CAM_CC_CCI_1_CLK 9
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#define CAM_CC_CCI_1_CLK_SRC 10
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#define CAM_CC_CORE_AHB_CLK 11
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#define CAM_CC_CPAS_AHB_CLK 12
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#define CAM_CC_CPHY_RX_CLK_SRC 13
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#define CAM_CC_CSI0PHYTIMER_CLK 14
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 15
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#define CAM_CC_CSI1PHYTIMER_CLK 16
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 17
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#define CAM_CC_CSI2PHYTIMER_CLK 18
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 19
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#define CAM_CC_CSI3PHYTIMER_CLK 20
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 21
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#define CAM_CC_CSIPHY0_CLK 22
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#define CAM_CC_CSIPHY1_CLK 23
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#define CAM_CC_CSIPHY2_CLK 24
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#define CAM_CC_CSIPHY3_CLK 25
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#define CAM_CC_FAST_AHB_CLK_SRC 26
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#define CAM_CC_ICP_APB_CLK 27
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#define CAM_CC_ICP_ATB_CLK 28
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#define CAM_CC_ICP_CLK 29
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#define CAM_CC_ICP_CLK_SRC 30
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#define CAM_CC_ICP_CTI_CLK 31
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#define CAM_CC_ICP_TS_CLK 32
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#define CAM_CC_IFE_0_AXI_CLK 33
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#define CAM_CC_IFE_0_CLK 34
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#define CAM_CC_IFE_0_CLK_SRC 35
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#define CAM_CC_IFE_0_CPHY_RX_CLK 36
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#define CAM_CC_IFE_0_CSID_CLK 37
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#define CAM_CC_IFE_0_CSID_CLK_SRC 38
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#define CAM_CC_IFE_0_DSP_CLK 39
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#define CAM_CC_IFE_1_AXI_CLK 40
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#define CAM_CC_IFE_1_CLK 41
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#define CAM_CC_IFE_1_CLK_SRC 42
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#define CAM_CC_IFE_1_CPHY_RX_CLK 43
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#define CAM_CC_IFE_1_CSID_CLK 44
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#define CAM_CC_IFE_1_CSID_CLK_SRC 45
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#define CAM_CC_IFE_1_DSP_CLK 46
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#define CAM_CC_IFE_LITE_CLK 47
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#define CAM_CC_IFE_LITE_CLK_SRC 48
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#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
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#define CAM_CC_IFE_LITE_CSID_CLK 50
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#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
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#define CAM_CC_IPE_0_AHB_CLK 52
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#define CAM_CC_IPE_0_AREG_CLK 53
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#define CAM_CC_IPE_0_AXI_CLK 54
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#define CAM_CC_IPE_0_CLK 55
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#define CAM_CC_IPE_0_CLK_SRC 56
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#define CAM_CC_JPEG_CLK 57
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#define CAM_CC_JPEG_CLK_SRC 58
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#define CAM_CC_LRME_CLK 59
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#define CAM_CC_LRME_CLK_SRC 60
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#define CAM_CC_MCLK0_CLK 61
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#define CAM_CC_MCLK0_CLK_SRC 62
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#define CAM_CC_MCLK1_CLK 63
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#define CAM_CC_MCLK1_CLK_SRC 64
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#define CAM_CC_MCLK2_CLK 65
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#define CAM_CC_MCLK2_CLK_SRC 66
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#define CAM_CC_MCLK3_CLK 67
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#define CAM_CC_MCLK3_CLK_SRC 68
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#define CAM_CC_MCLK4_CLK 69
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#define CAM_CC_MCLK4_CLK_SRC 70
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#define CAM_CC_BPS_AHB_CLK 71
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#define CAM_CC_BPS_AREG_CLK 72
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#define CAM_CC_BPS_AXI_CLK 73
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#define CAM_CC_BPS_CLK 74
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#define CAM_CC_BPS_CLK_SRC 75
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#define CAM_CC_SLOW_AHB_CLK_SRC 76
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#define CAM_CC_SOC_AHB_CLK 77
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#define CAM_CC_SYS_TMR_CLK 78
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/* CAM_CC power domains */
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#define BPS_GDSC 0
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#define IFE_0_GDSC 1
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#define IFE_1_GDSC 2
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#define IPE_0_GDSC 3
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#define TITAN_TOP_GDSC 4
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_CAMNOC_BCR 1
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#define CAM_CC_CCI_0_BCR 2
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#define CAM_CC_CCI_1_BCR 3
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#define CAM_CC_CPAS_BCR 4
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#define CAM_CC_CSI0PHY_BCR 5
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#define CAM_CC_CSI1PHY_BCR 6
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#define CAM_CC_CSI2PHY_BCR 7
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#define CAM_CC_CSI3PHY_BCR 8
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#define CAM_CC_ICP_BCR 9
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#define CAM_CC_IFE_0_BCR 10
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#define CAM_CC_IFE_1_BCR 11
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#define CAM_CC_IFE_LITE_BCR 12
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#define CAM_CC_IPE_0_BCR 13
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#define CAM_CC_JPEG_BCR 14
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#define CAM_CC_LRME_BCR 15
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#define CAM_CC_MCLK0_BCR 16
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#define CAM_CC_MCLK1_BCR 17
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#define CAM_CC_MCLK2_BCR 18
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#define CAM_CC_MCLK3_BCR 19
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#define CAM_CC_MCLK4_BCR 20
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#define CAM_CC_TITAN_TOP_BCR 21
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#endif
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