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f40c467523
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
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#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
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/* CAM_CC clock registers */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_AREG_CLK 1
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#define CAM_CC_BPS_AXI_CLK 2
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#define CAM_CC_BPS_CLK 3
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#define CAM_CC_BPS_CLK_SRC 4
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#define CAM_CC_CAMNOC_ATB_CLK 5
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#define CAM_CC_CAMNOC_AXI_CLK 6
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#define CAM_CC_CCI_CLK 7
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#define CAM_CC_CCI_CLK_SRC 8
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#define CAM_CC_CPAS_AHB_CLK 9
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#define CAM_CC_CPHY_RX_CLK_SRC 10
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#define CAM_CC_CSI0PHYTIMER_CLK 11
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
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#define CAM_CC_CSI1PHYTIMER_CLK 13
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
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#define CAM_CC_CSI2PHYTIMER_CLK 15
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
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#define CAM_CC_CSI3PHYTIMER_CLK 17
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
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#define CAM_CC_CSIPHY0_CLK 19
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#define CAM_CC_CSIPHY1_CLK 20
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#define CAM_CC_CSIPHY2_CLK 21
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#define CAM_CC_CSIPHY3_CLK 22
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#define CAM_CC_FAST_AHB_CLK_SRC 23
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#define CAM_CC_FD_CORE_CLK 24
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#define CAM_CC_FD_CORE_CLK_SRC 25
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#define CAM_CC_FD_CORE_UAR_CLK 26
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#define CAM_CC_ICP_APB_CLK 27
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#define CAM_CC_ICP_ATB_CLK 28
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#define CAM_CC_ICP_CLK 29
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#define CAM_CC_ICP_CLK_SRC 30
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#define CAM_CC_ICP_CTI_CLK 31
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#define CAM_CC_ICP_TS_CLK 32
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#define CAM_CC_IFE_0_AXI_CLK 33
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#define CAM_CC_IFE_0_CLK 34
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#define CAM_CC_IFE_0_CLK_SRC 35
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#define CAM_CC_IFE_0_CPHY_RX_CLK 36
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#define CAM_CC_IFE_0_CSID_CLK 37
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#define CAM_CC_IFE_0_CSID_CLK_SRC 38
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#define CAM_CC_IFE_0_DSP_CLK 39
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#define CAM_CC_IFE_1_AXI_CLK 40
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#define CAM_CC_IFE_1_CLK 41
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#define CAM_CC_IFE_1_CLK_SRC 42
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#define CAM_CC_IFE_1_CPHY_RX_CLK 43
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#define CAM_CC_IFE_1_CSID_CLK 44
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#define CAM_CC_IFE_1_CSID_CLK_SRC 45
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#define CAM_CC_IFE_1_DSP_CLK 46
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#define CAM_CC_IFE_LITE_CLK 47
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#define CAM_CC_IFE_LITE_CLK_SRC 48
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#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
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#define CAM_CC_IFE_LITE_CSID_CLK 50
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#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
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#define CAM_CC_IPE_0_AHB_CLK 52
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#define CAM_CC_IPE_0_AREG_CLK 53
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#define CAM_CC_IPE_0_AXI_CLK 54
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#define CAM_CC_IPE_0_CLK 55
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#define CAM_CC_IPE_0_CLK_SRC 56
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#define CAM_CC_IPE_1_AHB_CLK 57
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#define CAM_CC_IPE_1_AREG_CLK 58
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#define CAM_CC_IPE_1_AXI_CLK 59
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#define CAM_CC_IPE_1_CLK 60
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#define CAM_CC_IPE_1_CLK_SRC 61
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#define CAM_CC_JPEG_CLK 62
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#define CAM_CC_JPEG_CLK_SRC 63
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#define CAM_CC_LRME_CLK 64
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#define CAM_CC_LRME_CLK_SRC 65
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#define CAM_CC_MCLK0_CLK 66
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#define CAM_CC_MCLK0_CLK_SRC 67
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#define CAM_CC_MCLK1_CLK 68
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#define CAM_CC_MCLK1_CLK_SRC 69
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#define CAM_CC_MCLK2_CLK 70
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#define CAM_CC_MCLK2_CLK_SRC 71
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#define CAM_CC_MCLK3_CLK 72
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#define CAM_CC_MCLK3_CLK_SRC 73
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#define CAM_CC_PLL0 74
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#define CAM_CC_PLL0_OUT_EVEN 75
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#define CAM_CC_PLL1 76
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#define CAM_CC_PLL1_OUT_EVEN 77
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#define CAM_CC_PLL2 78
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#define CAM_CC_PLL2_OUT_EVEN 79
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#define CAM_CC_PLL3 80
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#define CAM_CC_PLL3_OUT_EVEN 81
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#define CAM_CC_SLOW_AHB_CLK_SRC 82
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#define CAM_CC_SOC_AHB_CLK 83
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#define CAM_CC_SYS_TMR_CLK 84
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/* CAM_CC Resets */
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#define TITAN_CAM_CC_CCI_BCR 0
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#define TITAN_CAM_CC_CPAS_BCR 1
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#define TITAN_CAM_CC_CSI0PHY_BCR 2
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#define TITAN_CAM_CC_CSI1PHY_BCR 3
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#define TITAN_CAM_CC_CSI2PHY_BCR 4
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#define TITAN_CAM_CC_MCLK0_BCR 5
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#define TITAN_CAM_CC_MCLK1_BCR 6
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#define TITAN_CAM_CC_MCLK2_BCR 7
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#define TITAN_CAM_CC_MCLK3_BCR 8
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#define TITAN_CAM_CC_TITAN_TOP_BCR 9
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/* CAM_CC GDSCRs */
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#define BPS_GDSC 0
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#define IPE_0_GDSC 1
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#define IPE_1_GDSC 2
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#define IFE_0_GDSC 3
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#define IFE_1_GDSC 4
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#define TITAN_TOP_GDSC 5
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#endif
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