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6faa7e4ddc
Add device tree bindings for global clock controller on MDM9607 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210313020310.386152-1-konrad.dybcio@somainline.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H
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#define _DT_BINDINGS_CLK_MSM_GCC_9607_H
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#define GPLL0 0
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#define GPLL0_EARLY 1
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#define GPLL1 2
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#define GPLL1_VOTE 3
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#define GPLL2 4
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#define GPLL2_EARLY 5
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#define PCNOC_BFDCD_CLK_SRC 6
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#define SYSTEM_NOC_BFDCD_CLK_SRC 7
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#define GCC_SMMU_CFG_CLK 8
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#define APSS_AHB_CLK_SRC 9
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#define GCC_QDSS_DAP_CLK 10
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22
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#define BLSP1_UART1_APPS_CLK_SRC 23
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#define BLSP1_UART2_APPS_CLK_SRC 24
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#define CRYPTO_CLK_SRC 25
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#define GP1_CLK_SRC 26
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#define GP2_CLK_SRC 27
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#define GP3_CLK_SRC 28
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#define PDM2_CLK_SRC 29
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#define SDCC1_APPS_CLK_SRC 30
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#define SDCC2_APPS_CLK_SRC 31
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#define APSS_TCU_CLK_SRC 32
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#define USB_HS_SYSTEM_CLK_SRC 33
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#define GCC_BLSP1_AHB_CLK 34
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#define GCC_BLSP1_SLEEP_CLK 35
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 44
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 45
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 46
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 47
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#define GCC_BLSP1_UART1_APPS_CLK 48
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#define GCC_BLSP1_UART2_APPS_CLK 49
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#define GCC_BOOT_ROM_AHB_CLK 50
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#define GCC_CRYPTO_AHB_CLK 51
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#define GCC_CRYPTO_AXI_CLK 52
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#define GCC_CRYPTO_CLK 53
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#define GCC_GP1_CLK 54
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#define GCC_GP2_CLK 55
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#define GCC_GP3_CLK 56
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#define GCC_MSS_CFG_AHB_CLK 57
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#define GCC_PDM2_CLK 58
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#define GCC_PDM_AHB_CLK 59
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#define GCC_PRNG_AHB_CLK 60
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#define GCC_SDCC1_AHB_CLK 61
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#define GCC_SDCC1_APPS_CLK 62
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#define GCC_SDCC2_AHB_CLK 63
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#define GCC_SDCC2_APPS_CLK 64
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#define GCC_USB2A_PHY_SLEEP_CLK 65
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#define GCC_USB_HS_AHB_CLK 66
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#define GCC_USB_HS_SYSTEM_CLK 67
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#define GCC_APSS_TCU_CLK 68
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#define GCC_MSS_Q6_BIMC_AXI_CLK 69
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#define BIMC_PLL 70
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#define BIMC_PLL_VOTE 71
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#define BIMC_DDR_CLK_SRC 72
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#define BLSP1_UART3_APPS_CLK_SRC 73
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#define BLSP1_UART4_APPS_CLK_SRC 74
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#define BLSP1_UART5_APPS_CLK_SRC 75
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#define BLSP1_UART6_APPS_CLK_SRC 76
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#define GCC_BLSP1_UART3_APPS_CLK 77
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#define GCC_BLSP1_UART4_APPS_CLK 78
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#define GCC_BLSP1_UART5_APPS_CLK 79
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#define GCC_BLSP1_UART6_APPS_CLK 80
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#define GCC_APSS_AHB_CLK 81
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#define GCC_APSS_AXI_CLK 82
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#define GCC_USB_HS_PHY_CFG_AHB_CLK 83
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#define GCC_USB_HSIC_CLK_SRC 84
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#define GCC_USB_HSIC_IO_CAL_CLK_SRC 85
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#define GCC_USB_HSIC_SYSTEM_CLK_SRC 86
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/* Resets */
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#define USB2_HS_PHY_ONLY_BCR 0
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#define QUSB2_PHY_BCR 1
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#define GCC_MSS_RESTART 2
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#define USB_HS_HSIC_BCR 3
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#define USB_HS_BCR 4
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#endif
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