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fa2d185f75
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a779A0 CPG Core Clocks */
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#define R8A779A0_CLK_Z0 0
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#define R8A779A0_CLK_ZX 1
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#define R8A779A0_CLK_Z1 2
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#define R8A779A0_CLK_ZR 3
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#define R8A779A0_CLK_ZS 4
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#define R8A779A0_CLK_ZT 5
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#define R8A779A0_CLK_ZTR 6
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#define R8A779A0_CLK_S1D1 7
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#define R8A779A0_CLK_S1D2 8
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#define R8A779A0_CLK_S1D4 9
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#define R8A779A0_CLK_S1D8 10
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#define R8A779A0_CLK_S1D12 11
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#define R8A779A0_CLK_S3D1 12
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#define R8A779A0_CLK_S3D2 13
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#define R8A779A0_CLK_S3D4 14
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#define R8A779A0_CLK_LB 15
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#define R8A779A0_CLK_CP 16
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#define R8A779A0_CLK_CL 17
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#define R8A779A0_CLK_CL16MCK 18
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#define R8A779A0_CLK_ZB30 19
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#define R8A779A0_CLK_ZB30D2 20
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#define R8A779A0_CLK_ZB30D4 21
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#define R8A779A0_CLK_ZB31 22
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#define R8A779A0_CLK_ZB31D2 23
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#define R8A779A0_CLK_ZB31D4 24
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#define R8A779A0_CLK_SD0H 25
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#define R8A779A0_CLK_SD0 26
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#define R8A779A0_CLK_RPC 27
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#define R8A779A0_CLK_RPCD2 28
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#define R8A779A0_CLK_MSO 29
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#define R8A779A0_CLK_CANFD 30
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#define R8A779A0_CLK_CSI0 31
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#define R8A779A0_CLK_FRAY 32
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#define R8A779A0_CLK_DSI 33
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#define R8A779A0_CLK_VIP 34
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#define R8A779A0_CLK_ADGH 35
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#define R8A779A0_CLK_CNNDSP 36
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#define R8A779A0_CLK_ICU 37
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#define R8A779A0_CLK_ICUD2 38
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#define R8A779A0_CLK_VCBUS 39
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#define R8A779A0_CLK_CBFUSA 40
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#define R8A779A0_CLK_R 41
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#define R8A779A0_CLK_OSC 42
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#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
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