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1dccb5ec01
Adding documentation and dt-bindings file which contains MIO pin configuration defines for Xilinx ZynqMP pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1618485193-5403-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
19 lines
449 B
C
19 lines
449 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MIO pin configuration defines for Xilinx ZynqMP
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*
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* Copyright (C) 2020 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
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#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
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/* Bit value for different voltage levels */
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#define IO_STANDARD_LVCMOS33 0
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#define IO_STANDARD_LVCMOS18 1
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/* Bit values for Slew Rates */
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#define SLEW_RATE_FAST 0
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#define SLEW_RATE_SLOW 1
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#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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