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9efa0c1a50
It requires a separate debugfs attribute to expose lpsp status to user space, as there may be display less configuration without any valid connected output, those configuration will not be able to test lpsp status, if lpsp status exposed from a connector based debugfs attribute. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200415170555.15531-5-anshuman.gupta@intel.com
330 lines
9.9 KiB
C
330 lines
9.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_POWER_H__
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#define __INTEL_DISPLAY_POWER_H__
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#include "intel_display.h"
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#include "intel_runtime_pm.h"
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#include "i915_reg.h"
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struct drm_i915_private;
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struct intel_encoder;
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enum intel_display_power_domain {
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POWER_DOMAIN_DISPLAY_CORE,
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POWER_DOMAIN_PIPE_A,
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POWER_DOMAIN_PIPE_B,
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POWER_DOMAIN_PIPE_C,
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POWER_DOMAIN_PIPE_D,
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POWER_DOMAIN_PIPE_A_PANEL_FITTER,
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POWER_DOMAIN_PIPE_B_PANEL_FITTER,
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POWER_DOMAIN_PIPE_C_PANEL_FITTER,
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POWER_DOMAIN_PIPE_D_PANEL_FITTER,
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POWER_DOMAIN_TRANSCODER_A,
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POWER_DOMAIN_TRANSCODER_B,
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POWER_DOMAIN_TRANSCODER_C,
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POWER_DOMAIN_TRANSCODER_D,
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POWER_DOMAIN_TRANSCODER_EDP,
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/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
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POWER_DOMAIN_TRANSCODER_VDSC_PW2,
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POWER_DOMAIN_TRANSCODER_DSI_A,
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POWER_DOMAIN_TRANSCODER_DSI_C,
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POWER_DOMAIN_PORT_DDI_A_LANES,
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POWER_DOMAIN_PORT_DDI_B_LANES,
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POWER_DOMAIN_PORT_DDI_C_LANES,
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POWER_DOMAIN_PORT_DDI_D_LANES,
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POWER_DOMAIN_PORT_DDI_E_LANES,
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POWER_DOMAIN_PORT_DDI_F_LANES,
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POWER_DOMAIN_PORT_DDI_G_LANES,
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POWER_DOMAIN_PORT_DDI_H_LANES,
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POWER_DOMAIN_PORT_DDI_I_LANES,
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POWER_DOMAIN_PORT_DDI_A_IO,
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POWER_DOMAIN_PORT_DDI_B_IO,
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POWER_DOMAIN_PORT_DDI_C_IO,
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POWER_DOMAIN_PORT_DDI_D_IO,
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POWER_DOMAIN_PORT_DDI_E_IO,
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POWER_DOMAIN_PORT_DDI_F_IO,
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POWER_DOMAIN_PORT_DDI_G_IO,
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POWER_DOMAIN_PORT_DDI_H_IO,
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POWER_DOMAIN_PORT_DDI_I_IO,
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POWER_DOMAIN_PORT_DSI,
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POWER_DOMAIN_PORT_CRT,
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POWER_DOMAIN_PORT_OTHER,
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POWER_DOMAIN_VGA,
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POWER_DOMAIN_AUDIO,
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POWER_DOMAIN_AUX_A,
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POWER_DOMAIN_AUX_B,
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POWER_DOMAIN_AUX_C,
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POWER_DOMAIN_AUX_D,
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POWER_DOMAIN_AUX_E,
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POWER_DOMAIN_AUX_F,
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POWER_DOMAIN_AUX_G,
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POWER_DOMAIN_AUX_H,
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POWER_DOMAIN_AUX_I,
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POWER_DOMAIN_AUX_IO_A,
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POWER_DOMAIN_AUX_C_TBT,
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POWER_DOMAIN_AUX_D_TBT,
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POWER_DOMAIN_AUX_E_TBT,
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POWER_DOMAIN_AUX_F_TBT,
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POWER_DOMAIN_AUX_G_TBT,
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POWER_DOMAIN_AUX_H_TBT,
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POWER_DOMAIN_AUX_I_TBT,
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POWER_DOMAIN_GMBUS,
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POWER_DOMAIN_MODESET,
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POWER_DOMAIN_GT_IRQ,
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POWER_DOMAIN_DPLL_DC_OFF,
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POWER_DOMAIN_INIT,
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POWER_DOMAIN_NUM,
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};
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/*
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* i915_power_well_id:
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*
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* IDs used to look up power wells. Power wells accessed directly bypassing
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* the power domains framework must be assigned a unique ID. The rest of power
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* wells must be assigned DISP_PW_ID_NONE.
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*/
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enum i915_power_well_id {
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DISP_PW_ID_NONE,
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VLV_DISP_PW_DISP2D,
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BXT_DISP_PW_DPIO_CMN_A,
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VLV_DISP_PW_DPIO_CMN_BC,
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GLK_DISP_PW_DPIO_CMN_C,
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CHV_DISP_PW_DPIO_CMN_D,
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HSW_DISP_PW_GLOBAL,
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SKL_DISP_PW_MISC_IO,
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SKL_DISP_PW_1,
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SKL_DISP_PW_2,
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ICL_DISP_PW_3,
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SKL_DISP_DC_OFF,
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};
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#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
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#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
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((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
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((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
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(tran) + POWER_DOMAIN_TRANSCODER_A)
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struct i915_power_well;
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struct i915_power_well_ops {
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/*
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* Synchronize the well's hw state to match the current sw state, for
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* example enable/disable it based on the current refcount. Called
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* during driver init and resume time, possibly after first calling
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* the enable/disable handlers.
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*/
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void (*sync_hw)(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well);
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/*
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* Enable the well and resources that depend on it (for example
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* interrupts located on the well). Called after the 0->1 refcount
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* transition.
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*/
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void (*enable)(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well);
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/*
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* Disable the well and resources that depend on it. Called after
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* the 1->0 refcount transition.
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*/
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void (*disable)(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well);
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/* Returns the hw enabled state. */
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bool (*is_enabled)(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well);
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};
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struct i915_power_well_regs {
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i915_reg_t bios;
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i915_reg_t driver;
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i915_reg_t kvmr;
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i915_reg_t debug;
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};
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/* Power well structure for haswell */
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struct i915_power_well_desc {
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const char *name;
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bool always_on;
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u64 domains;
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/* unique identifier for this power well */
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enum i915_power_well_id id;
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/*
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* Arbitraty data associated with this power well. Platform and power
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* well specific.
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*/
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union {
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struct {
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/*
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* request/status flag index in the PUNIT power well
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* control/status registers.
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*/
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u8 idx;
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} vlv;
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struct {
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enum dpio_phy phy;
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} bxt;
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struct {
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const struct i915_power_well_regs *regs;
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/*
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* request/status flag index in the power well
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* constrol/status registers.
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*/
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u8 idx;
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/* Mask of pipes whose IRQ logic is backed by the pw */
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u8 irq_pipe_mask;
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/* The pw is backing the VGA functionality */
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bool has_vga:1;
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bool has_fuses:1;
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/*
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* The pw is for an ICL+ TypeC PHY port in
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* Thunderbolt mode.
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*/
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bool is_tc_tbt:1;
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} hsw;
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};
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const struct i915_power_well_ops *ops;
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};
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struct i915_power_well {
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const struct i915_power_well_desc *desc;
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/* power well enable/disable usage count */
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int count;
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/* cached hw enabled state */
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bool hw_enabled;
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};
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struct i915_power_domains {
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/*
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* Power wells needed for initialization at driver init and suspend
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* time are on. They are kept on until after the first modeset.
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*/
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bool initializing;
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bool display_core_suspended;
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int power_well_count;
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intel_wakeref_t wakeref;
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struct mutex lock;
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int domain_use_count[POWER_DOMAIN_NUM];
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struct delayed_work async_put_work;
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intel_wakeref_t async_put_wakeref;
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u64 async_put_domains[2];
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struct i915_power_well *power_wells;
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};
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#define for_each_power_domain(domain, mask) \
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for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
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for_each_if(BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well) \
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for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
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(__power_well) - (__dev_priv)->power_domains.power_wells < \
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(__dev_priv)->power_domains.power_well_count; \
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(__power_well)++)
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#define for_each_power_well_reverse(__dev_priv, __power_well) \
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for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
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(__dev_priv)->power_domains.power_well_count - 1; \
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(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
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(__power_well)--)
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#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
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for_each_power_well(__dev_priv, __power_well) \
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for_each_if((__power_well)->desc->domains & (__domain_mask))
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#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
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for_each_power_well_reverse(__dev_priv, __power_well) \
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for_each_if((__power_well)->desc->domains & (__domain_mask))
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int intel_power_domains_init(struct drm_i915_private *dev_priv);
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void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
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void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
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void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
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void intel_power_domains_enable(struct drm_i915_private *dev_priv);
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void intel_power_domains_disable(struct drm_i915_private *dev_priv);
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void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
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enum i915_drm_suspend_mode);
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void intel_power_domains_resume(struct drm_i915_private *dev_priv);
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void intel_display_power_suspend_late(struct drm_i915_private *i915);
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void intel_display_power_resume_early(struct drm_i915_private *i915);
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void intel_display_power_suspend(struct drm_i915_private *i915);
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void intel_display_power_resume(struct drm_i915_private *i915);
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void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
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u32 state);
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const char *
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intel_display_power_domain_str(enum intel_display_power_domain domain);
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bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
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enum i915_power_well_id power_well_id);
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bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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intel_wakeref_t
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intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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void __intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref);
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void intel_display_power_flush_work(struct drm_i915_private *i915);
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
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void intel_display_power_put(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref);
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static inline void
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intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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__intel_display_power_put_async(i915, domain, wakeref);
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}
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#else
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static inline void
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intel_display_power_put(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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intel_display_power_put_unchecked(i915, domain);
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}
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static inline void
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intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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__intel_display_power_put_async(i915, domain, -1);
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}
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#endif
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enum dbuf_slice {
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DBUF_S1,
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DBUF_S2,
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};
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#define with_intel_display_power(i915, domain, wf) \
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for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
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intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
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void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
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u8 req_slices);
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void chv_phy_powergate_lanes(struct intel_encoder *encoder,
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bool override, unsigned int mask);
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bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
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enum dpio_channel ch, bool override);
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#endif /* __INTEL_DISPLAY_POWER_H__ */
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