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This is the third and smallest of the SoC specific updates. Changes include: * SMP support for the Xilinx zynq platform * Smaller imx changes * LPAE support for mvebu * Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUYgifmCrR//JCVInAQLZ6A//VD38ocUx9RPC8rOgrkzQxcMTh3wFghoA BVvS8fcAmhZYA5+GpTYBm+5XH2Jvu6Pv0hrba8TOeEhyZJxiWA6vg0cWWmnvZLDC Q0uubhqIhv32I2Oq4uJb/VyzcCrQFrnjhw9HHphy7YlGKKBUFWrbgTaOypwbgXr9 DnB7u04DvaKcUjZb4Y0HaUDM7qWMFDPbKKF5WMZPqjocnjsiBQ2JMw+2KByliWR3 mCI+FdickpDYSVp9V9iRM6F73cItknjZIzQs1RYg/GSuPSWkWTdfzE1Blk/561Fo QDrNDhnXHlt+bmQRKGWel2gDWBZW47Wj+XkjGpWDFh+e/l3vNJq0hrzXizuRCLSw /2VefXyd3jNj8UWL3+GCA4dnw8fx14dgfNJ2iu7kg6l4ggwpJ05ToxabkLFlTRwy LloDFjswiTBi75YdQRQCV/95NIxvIQIkbytPrk5zQWVwg8ZXoicgzRRUL5gifLh+ WE+zaY/A5e1fXN/XS70hvbp2ROZtfGOdunUR9XFR8KNqDoJDlqtrlV3Pjh75YY8G JUmCKQjzfubr5WHskPBGCtsSb1455MEIFVANEtlJyOEKp6ytXfpVvrrZtAvmD6Ep 07dOqOgflnuZPk7H0JOf7mTf9L+fmNp4ubjRqcs9ZfPsEGoQFqBtpLF6JQbxUYGd j69lW3jEM3o= =rQsu -----END PGP SIGNATURE----- Merge tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates (part 3) from Arnd Bergmann: "This is the third and smallest of the SoC specific updates. Changes include: - SMP support for the Xilinx zynq platform - Smaller imx changes - LPAE support for mvebu - Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more." * tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: imx: reset_controller may be disabled ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ...
156 lines
3.6 KiB
C
156 lines
3.6 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#include <linux/smp.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#define SRC_SCR 0x000
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#define SRC_GPR1 0x020
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#define BP_SRC_SCR_WARM_RESET_ENABLE 0
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#define BP_SRC_SCR_SW_GPU_RST 1
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#define BP_SRC_SCR_SW_VPU_RST 2
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#define BP_SRC_SCR_SW_IPU1_RST 3
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#define BP_SRC_SCR_SW_OPEN_VG_RST 4
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#define BP_SRC_SCR_SW_IPU2_RST 12
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#define BP_SRC_SCR_CORE1_RST 14
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#define BP_SRC_SCR_CORE1_ENABLE 22
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static void __iomem *src_base;
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static DEFINE_SPINLOCK(scr_lock);
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static const int sw_reset_bits[5] = {
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BP_SRC_SCR_SW_GPU_RST,
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BP_SRC_SCR_SW_VPU_RST,
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BP_SRC_SCR_SW_IPU1_RST,
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BP_SRC_SCR_SW_OPEN_VG_RST,
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BP_SRC_SCR_SW_IPU2_RST
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};
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static int imx_src_reset_module(struct reset_controller_dev *rcdev,
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unsigned long sw_reset_idx)
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{
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unsigned long timeout;
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unsigned long flags;
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int bit;
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u32 val;
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if (!src_base)
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return -ENODEV;
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if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
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return -EINVAL;
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bit = 1 << sw_reset_bits[sw_reset_idx];
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spin_lock_irqsave(&scr_lock, flags);
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val = readl_relaxed(src_base + SRC_SCR);
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val |= bit;
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock_irqrestore(&scr_lock, flags);
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timeout = jiffies + msecs_to_jiffies(1000);
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while (readl(src_base + SRC_SCR) & bit) {
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if (time_after(jiffies, timeout))
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return -ETIME;
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cpu_relax();
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}
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return 0;
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}
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static struct reset_control_ops imx_src_ops = {
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.reset = imx_src_reset_module,
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};
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static struct reset_controller_dev imx_reset_controller = {
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.ops = &imx_src_ops,
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.nr_resets = ARRAY_SIZE(sw_reset_bits),
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};
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void imx_enable_cpu(int cpu, bool enable)
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{
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u32 mask, val;
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cpu = cpu_logical_map(cpu);
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mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val = enable ? val | mask : val & ~mask;
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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}
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void imx_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(virt_to_phys(jump_addr),
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src_base + SRC_GPR1 + cpu * 8);
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}
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u32 imx_get_cpu_arg(int cpu)
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{
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cpu = cpu_logical_map(cpu);
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return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
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}
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void imx_set_cpu_arg(int cpu, u32 arg)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
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}
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void imx_src_prepare_restart(void)
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{
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u32 val;
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/* clear enable bits of secondary cores */
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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/* clear persistent entry register of primary core */
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writel_relaxed(0, src_base + SRC_GPR1);
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}
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void __init imx_src_init(void)
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{
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struct device_node *np;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
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if (!np)
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return;
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src_base = of_iomap(np, 0);
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WARN_ON(!src_base);
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imx_reset_controller.of_node = np;
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if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
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reset_controller_register(&imx_reset_controller);
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/*
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* force warm reset sources to generate cold reset
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* for a more reliable restart
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*/
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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}
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