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33d5c01915
The Tegra114 is a quad cores SoC. Each core can be hotplugged including CPU0. The hotplug sequence can be controlled by setting event trigger in flow controller. Then the flow controller will take care all the power sequence that include CPU up and down. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
190 lines
4.6 KiB
ArmAsm
190 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include "fuse.h"
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#include "sleep.h"
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#include "flowctrl.h"
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#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra30_hotplug_shutdown(void)
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*
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* Powergates the current CPU.
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* Should never return.
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*/
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ENTRY(tegra30_hotplug_shutdown)
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/* Powergate this CPU */
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mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
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bl tegra30_cpu_shutdown
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mov pc, lr @ should never get here
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ENDPROC(tegra30_hotplug_shutdown)
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/*
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* tegra30_cpu_shutdown(unsigned long flags)
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*
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* Puts the current CPU in wait-for-event mode on the flow controller
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* and powergates it -- flags (in R0) indicate the request type.
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*
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* r10 = SoC ID
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* corrupts r0-r4, r10-r12
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*/
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ENTRY(tegra30_cpu_shutdown)
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cpu_id r3
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tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
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cmp r10, #TEGRA30
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bne _no_cpu0_chk @ It's not Tegra30
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cmp r3, #0
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moveq pc, lr @ Must never be called for CPU 0
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_no_cpu0_chk:
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ldr r12, =TEGRA_FLOW_CTRL_VIRT
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cpu_to_csr_reg r1, r3
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add r1, r1, r12 @ virtual CSR address for this CPU
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cpu_to_halt_reg r2, r3
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add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
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/*
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* Clear this CPU's "event" and "interrupt" flags and power gate
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* it when halting but not before it is in the "WFE" state.
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*/
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movw r12, \
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FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
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FLOW_CTRL_CSR_ENABLE
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cmp r10, #TEGRA30
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moveq r4, #(1 << 4) @ wfe bitmap
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movne r4, #(1 << 8) @ wfi bitmap
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ARM( orr r12, r12, r4, lsl r3 )
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THUMB( lsl r4, r4, r3 )
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THUMB( orr r12, r12, r4 )
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str r12, [r1]
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/* Halt this CPU. */
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mov r3, #0x400
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delay_1:
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subs r3, r3, #1 @ delay as a part of wfe war.
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bge delay_1;
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cpsid a @ disable imprecise aborts.
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ldr r3, [r1] @ read CSR
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str r3, [r1] @ clear CSR
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tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
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beq flow_ctrl_setting_for_lp2
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/* flow controller set up for hotplug */
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mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
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b flow_ctrl_done
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flow_ctrl_setting_for_lp2:
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/* flow controller set up for LP2 */
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cmp r10, #TEGRA30
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moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
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movne r3, #FLOW_CTRL_WAITEVENT
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flow_ctrl_done:
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cmp r10, #TEGRA30
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str r3, [r2]
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ldr r0, [r2]
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b wfe_war
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__cpu_reset_again:
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dsb
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.align 5
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wfeeq @ CPU should be power gated here
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wfine
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wfe_war:
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b __cpu_reset_again
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/*
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* 38 nop's, which fills reset of wfe cache line and
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* 4 more cachelines with nop
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*/
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.rept 38
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nop
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.endr
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b . @ should never get here
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ENDPROC(tegra30_cpu_shutdown)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
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*
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* Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
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*/
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ENTRY(tegra30_sleep_cpu_secondary_finish)
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mov r7, lr
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/* Flush and disable the L1 data cache */
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bl tegra_disable_clean_inv_dcache
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/* Powergate this CPU. */
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mov r0, #0 @ power mode flags (!hotplug)
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bl tegra30_cpu_shutdown
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mov r0, #1 @ never return here
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mov pc, r7
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ENDPROC(tegra30_sleep_cpu_secondary_finish)
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/*
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* tegra30_tear_down_cpu
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*
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* Switches the CPU to enter sleep.
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*/
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ENTRY(tegra30_tear_down_cpu)
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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b tegra30_enter_sleep
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ENDPROC(tegra30_tear_down_cpu)
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/*
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* tegra30_enter_sleep
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*
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* uses flow controller to enter sleep state
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* executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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* executes from SDRAM with target state is LP2
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* r6 = TEGRA_FLOW_CTRL_BASE
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*/
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tegra30_enter_sleep:
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cpu_id r1
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cpu_to_csr_reg r2, r1
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ldr r0, [r6, r2]
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orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
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orr r0, r0, #FLOW_CTRL_CSR_ENABLE
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str r0, [r6, r2]
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mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
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orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
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cpu_to_halt_reg r2, r1
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str r0, [r6, r2]
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dsb
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ldr r0, [r6, r2] /* memory barrier */
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halted:
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isb
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dsb
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wfi /* CPU should be power gated here */
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/* !!!FIXME!!! Implement halt failure handler */
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b halted
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#endif
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