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c13ac55525
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Richard Weinberger <richard@nod.at>
94 lines
2.7 KiB
Text
94 lines
2.7 KiB
Text
Device tree bindings for Texas instruments Davinci/Keystone NAND controller
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This file provides information, what the device node for the davinci/keystone
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NAND interface contains.
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Documentation:
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Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
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Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
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Required properties:
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- compatible: "ti,davinci-nand"
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"ti,keystone-nand"
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- reg: Contains 2 offset/length values:
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- offset and length for the access window.
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- offset and length for accessing the AEMIF
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control registers.
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- ti,davinci-chipselect: number of chipselect. Indicates on the
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davinci_nand driver which chipselect is used
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for accessing the nand.
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Can be in the range [0-3].
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Recommended properties :
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- ti,davinci-mask-ale: mask for ALE. Needed for executing address
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x08.
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- ti,davinci-mask-cle: mask for CLE. Needed for executing command
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x10.
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- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
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addresses for given chipselect.
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- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
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- nand-bus-width: buswidth 8 or 16. If not present 8.
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- nand-on-flash-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Deprecated properties:
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- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
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- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Nand device bindings may contain additional sub-nodes describing partitions of
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the address space. See partition.txt for more detail. The NAND Flash timing
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values must be programmed in the chip select’s node of AEMIF
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memory-controller (see Documentation/devicetree/bindings/memory-controllers/
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davinci-aemif.txt).
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Example(da850 EVM ):
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nand_cs3@62000000 {
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compatible = "ti,davinci-nand";
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reg = <0x62000000 0x807ff
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0x68000000 0x8000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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nand-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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nand-on-flash-bbt;
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partition@180000 {
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label = "ubifs";
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reg = <0x180000 0x7e80000>;
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};
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};
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