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![Rafał Miłecki](/assets/img/avatar_default.png)
Broadocm updated their code, this may be needed for newer hardware or some corner cases. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
156 lines
3.6 KiB
C
156 lines
3.6 KiB
C
/*
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* Broadcom specific AMBA
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* Core ops
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
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u32 value, int timeout)
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{
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unsigned long deadline = jiffies + timeout;
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u32 val;
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do {
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val = bcma_aread32(core, reg);
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if ((val & mask) == value)
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return true;
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cpu_relax();
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udelay(10);
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} while (!time_after_eq(jiffies, deadline));
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bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
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return false;
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}
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bool bcma_core_is_enabled(struct bcma_device *core)
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{
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if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
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!= BCMA_IOCTL_CLK)
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return false;
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if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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return false;
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return true;
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}
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EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
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void bcma_core_disable(struct bcma_device *core, u32 flags)
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{
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if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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return;
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bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
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bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
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bcma_aread32(core, BCMA_RESET_CTL);
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udelay(1);
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bcma_awrite32(core, BCMA_IOCTL, flags);
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bcma_aread32(core, BCMA_IOCTL);
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udelay(10);
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}
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EXPORT_SYMBOL_GPL(bcma_core_disable);
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int bcma_core_enable(struct bcma_device *core, u32 flags)
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{
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bcma_core_disable(core, flags);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
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bcma_aread32(core, BCMA_IOCTL);
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bcma_awrite32(core, BCMA_RESET_CTL, 0);
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bcma_aread32(core, BCMA_RESET_CTL);
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udelay(1);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
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bcma_aread32(core, BCMA_IOCTL);
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udelay(1);
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcma_core_enable);
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void bcma_core_set_clockmode(struct bcma_device *core,
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enum bcma_clkmode clkmode)
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{
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u16 i;
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WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
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core->id.id != BCMA_CORE_PCIE &&
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core->id.id != BCMA_CORE_80211);
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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usleep_range(64, 300);
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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bcma_err(core->bus, "HT force timeout\n");
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break;
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case BCMA_CLKMODE_DYNAMIC:
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bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
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break;
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
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void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
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{
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u16 i;
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WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
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WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
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if (on) {
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bcma_set32(core, BCMA_CLKCTLST, req);
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for (i = 0; i < 10000; i++) {
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if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
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status) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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bcma_err(core->bus, "PLL enable timeout\n");
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} else {
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/*
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* Mask the PLL but don't wait for it to be disabled. PLL may be
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* shared between cores and will be still up if there is another
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* core using it.
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*/
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bcma_mask32(core, BCMA_CLKCTLST, ~req);
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bcma_read32(core, BCMA_CLKCTLST);
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
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u32 bcma_core_dma_translation(struct bcma_device *core)
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{
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switch (core->bus->hosttype) {
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case BCMA_HOSTTYPE_SOC:
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return 0;
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case BCMA_HOSTTYPE_PCI:
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if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
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return BCMA_DMA_TRANSLATION_DMA64_CMT;
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else
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return BCMA_DMA_TRANSLATION_DMA32_CMT;
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default:
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bcma_err(core->bus, "DMA translation unknown for host %d\n",
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core->bus->hosttype);
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}
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return BCMA_DMA_TRANSLATION_NONE;
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}
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EXPORT_SYMBOL(bcma_core_dma_translation);
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