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![Linus Torvalds](/assets/img/avatar_default.png)
This merge window brings a good size of cleanups on various platforms. Among the bigger ones: * Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. * OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. * Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. * Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJT5DYPAAoJEIwa5zzehBx37egQAIiatNiLLqZnfo3rwGADRz/a POfPovktj68aPcobyzoyhFtToMqGvi9PpysyFTIQD2HJFG+5BtiIAuqtg0875zDe EpBWgsfugrm0YktJWAtUerj60oAmNPbKfaEm1cOOWuM2lb2mV+QkRrwSTAgsqkT7 927BzMXKKBRPOVLL0RYhoF8EXa0Eg8kCqAHP8fJrzVYkRp+UrZJDnGiUP1XmWJN+ VXQMu5SEjcPMtqT7+tfX455RfREHJfBcJ1ZN/dPF8HMWDwClQG0lyc6hifh1MxwO 8DjIZNkfZeKqgDqVyC17re7pc7p8md5HL8WXbrKpK0A9vQ5bRexbPHxcwJ1T/C2Y 465H+st5XXbuzV1gbMwjK1/ycsH0tCyffckk8Yl/2e1Fs7GgPNbAELtTdl+5vV1Y xmDXkyo/9WlRM3LQ23IGKwW7VzN86EfWVuShssfro0fO7xDdb4OOYLdQI+4bCG+h ytQYun1vU32OEyNik5RVNQuZaMrv2c93a3bID4owwuPHPmYOPVUQaqnRX/0E51eA aHZYbk2GlUOV3Kq5aSS4iyLg1Yj+I9/NeH9U+A4nc+PQ5FlgGToaVSCuYuw4DqbP AAG+sqQHbkBMvDPobQz/yd1qZbAb4eLhGy11XK1t5S65rApWI55GwNXnvbyxqt8x wpmxJTASGxcfuZZgKXm7 =gbcE -----END PGP SIGNATURE----- Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
1296 lines
32 KiB
C
1296 lines
32 KiB
C
/*
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* IOMMU API for SMMU in Tegra30
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#define pr_fmt(fmt) "%s(): " fmt, __func__
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <linux/device.h>
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#include <linux/sched.h>
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#include <linux/iommu.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_iommu.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <soc/tegra/ahb.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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enum smmu_hwgrp {
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HWGRP_AFI,
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HWGRP_AVPC,
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HWGRP_DC,
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HWGRP_DCB,
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HWGRP_EPP,
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HWGRP_G2,
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HWGRP_HC,
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HWGRP_HDA,
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HWGRP_ISP,
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HWGRP_MPE,
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HWGRP_NV,
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HWGRP_NV2,
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HWGRP_PPCS,
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HWGRP_SATA,
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HWGRP_VDE,
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HWGRP_VI,
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HWGRP_COUNT,
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HWGRP_END = ~0,
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};
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#define HWG_AFI (1 << HWGRP_AFI)
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#define HWG_AVPC (1 << HWGRP_AVPC)
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#define HWG_DC (1 << HWGRP_DC)
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#define HWG_DCB (1 << HWGRP_DCB)
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#define HWG_EPP (1 << HWGRP_EPP)
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#define HWG_G2 (1 << HWGRP_G2)
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#define HWG_HC (1 << HWGRP_HC)
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#define HWG_HDA (1 << HWGRP_HDA)
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#define HWG_ISP (1 << HWGRP_ISP)
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#define HWG_MPE (1 << HWGRP_MPE)
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#define HWG_NV (1 << HWGRP_NV)
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#define HWG_NV2 (1 << HWGRP_NV2)
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#define HWG_PPCS (1 << HWGRP_PPCS)
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#define HWG_SATA (1 << HWGRP_SATA)
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#define HWG_VDE (1 << HWGRP_VDE)
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#define HWG_VI (1 << HWGRP_VI)
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/* bitmap of the page sizes currently supported */
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#define SMMU_IOMMU_PGSIZES (SZ_4K)
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#define SMMU_CONFIG 0x10
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#define SMMU_CONFIG_DISABLE 0
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#define SMMU_CONFIG_ENABLE 1
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/* REVISIT: To support multiple MCs */
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enum {
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_MC = 0,
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};
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enum {
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_TLB = 0,
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_PTC,
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};
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#define SMMU_CACHE_CONFIG_BASE 0x14
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#define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
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#define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
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#define SMMU_CACHE_CONFIG_STATS_SHIFT 31
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#define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
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#define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
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#define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
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#define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
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#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
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#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
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#define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
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#define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
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#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
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#define SMMU_PTB_ASID 0x1c
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#define SMMU_PTB_ASID_CURRENT_SHIFT 0
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#define SMMU_PTB_DATA 0x20
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#define SMMU_PTB_DATA_RESET_VAL 0
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#define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
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#define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
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#define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
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#define SMMU_TLB_FLUSH 0x30
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#define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
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#define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
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#define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
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#define SMMU_TLB_FLUSH_ASID_SHIFT 29
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#define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
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#define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
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#define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
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#define SMMU_PTC_FLUSH 0x34
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#define SMMU_PTC_FLUSH_TYPE_ALL 0
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#define SMMU_PTC_FLUSH_TYPE_ADR 1
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#define SMMU_PTC_FLUSH_ADR_SHIFT 4
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#define SMMU_ASID_SECURITY 0x38
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#define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
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#define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
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(SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
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#define SMMU_TRANSLATION_ENABLE_0 0x228
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#define SMMU_TRANSLATION_ENABLE_1 0x22c
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#define SMMU_TRANSLATION_ENABLE_2 0x230
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#define SMMU_AFI_ASID 0x238 /* PCIE */
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#define SMMU_AVPC_ASID 0x23c /* AVP */
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#define SMMU_DC_ASID 0x240 /* Display controller */
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#define SMMU_DCB_ASID 0x244 /* Display controller B */
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#define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
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#define SMMU_G2_ASID 0x24c /* 2D engine */
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#define SMMU_HC_ASID 0x250 /* Host1x */
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#define SMMU_HDA_ASID 0x254 /* High-def audio */
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#define SMMU_ISP_ASID 0x258 /* Image signal processor */
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#define SMMU_MPE_ASID 0x264 /* MPEG encoder */
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#define SMMU_NV_ASID 0x268 /* (3D) */
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#define SMMU_NV2_ASID 0x26c /* (3D) */
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#define SMMU_PPCS_ASID 0x270 /* AHB */
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#define SMMU_SATA_ASID 0x278 /* SATA */
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#define SMMU_VDE_ASID 0x27c /* Video decoder */
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#define SMMU_VI_ASID 0x280 /* Video input */
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#define SMMU_PDE_NEXT_SHIFT 28
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#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
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#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
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#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
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#define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
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#define SMMU_TLB_FLUSH_VA(iova, which) \
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((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
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SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
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SMMU_TLB_FLUSH_VA_MATCH_##which)
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#define SMMU_PTB_ASID_CUR(n) \
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((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
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#define SMMU_TLB_FLUSH_ASID_MATCH_disable \
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(SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
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SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
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#define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
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(SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
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SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000fffff
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
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#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
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#define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
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#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
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#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
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#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
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#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
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#define SMMU_MK_PDIR(page, attr) \
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((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) \
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(unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
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#define SMMU_EX_PTBL_PAGE(pde) \
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pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
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#define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
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#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
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#define SMMU_ASID_DISABLE 0
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#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
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#define NUM_SMMU_REG_BANKS 3
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#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
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#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
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#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
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#define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
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#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
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static const u32 smmu_hwgrp_asid_reg[] = {
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HWGRP_INIT(AFI),
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HWGRP_INIT(AVPC),
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HWGRP_INIT(DC),
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HWGRP_INIT(DCB),
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HWGRP_INIT(EPP),
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HWGRP_INIT(G2),
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HWGRP_INIT(HC),
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HWGRP_INIT(HDA),
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HWGRP_INIT(ISP),
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HWGRP_INIT(MPE),
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HWGRP_INIT(NV),
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HWGRP_INIT(NV2),
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HWGRP_INIT(PPCS),
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HWGRP_INIT(SATA),
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HWGRP_INIT(VDE),
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HWGRP_INIT(VI),
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};
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#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
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/*
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* Per client for address space
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*/
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struct smmu_client {
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struct device *dev;
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struct list_head list;
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struct smmu_as *as;
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u32 hwgrp;
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};
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/*
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* Per address space
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*/
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struct smmu_as {
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struct smmu_device *smmu; /* back pointer to container */
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unsigned int asid;
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spinlock_t lock; /* for pagetable */
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struct page *pdir_page;
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unsigned long pdir_attr;
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unsigned long pde_attr;
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unsigned long pte_attr;
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unsigned int *pte_count;
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struct list_head client;
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spinlock_t client_lock; /* for client list */
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};
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struct smmu_debugfs_info {
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struct smmu_device *smmu;
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int mc;
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int cache;
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};
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/*
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* Per SMMU device - IOMMU device
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*/
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struct smmu_device {
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void __iomem *regbase; /* register offset base */
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void __iomem **regs; /* register block start address array */
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void __iomem **rege; /* register block end address array */
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int nregs; /* number of register blocks */
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unsigned long iovmm_base; /* remappable base address */
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unsigned long page_count; /* total remappable size */
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spinlock_t lock;
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char *name;
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struct device *dev;
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struct page *avp_vector_page; /* dummy page shared by all AS's */
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/*
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* Register image savers for suspend/resume
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*/
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unsigned long translation_enable_0;
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unsigned long translation_enable_1;
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unsigned long translation_enable_2;
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unsigned long asid_security;
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struct dentry *debugfs_root;
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struct smmu_debugfs_info *debugfs_info;
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struct device_node *ahb;
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int num_as;
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struct smmu_as as[0]; /* Run-time allocated array */
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};
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static struct smmu_device *smmu_handle; /* unique for a system */
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/*
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* SMMU register accessors
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*/
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static bool inline smmu_valid_reg(struct smmu_device *smmu,
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void __iomem *addr)
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{
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int i;
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for (i = 0; i < smmu->nregs; i++) {
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if (addr < smmu->regs[i])
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break;
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if (addr <= smmu->rege[i])
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return true;
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}
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return false;
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}
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static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
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{
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void __iomem *addr = smmu->regbase + offs;
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BUG_ON(!smmu_valid_reg(smmu, addr));
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return readl(addr);
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}
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static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
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{
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void __iomem *addr = smmu->regbase + offs;
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BUG_ON(!smmu_valid_reg(smmu, addr));
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|
|
writel(val, addr);
|
|
}
|
|
|
|
#define VA_PAGE_TO_PA(va, page) \
|
|
(page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
|
|
|
|
#define FLUSH_CPU_DCACHE(va, page, size) \
|
|
do { \
|
|
unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
|
|
__cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
|
|
outer_flush_range(_pa_, _pa_+(size_t)(size)); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Any interaction between any block on PPSB and a block on APB or AHB
|
|
* must have these read-back barriers to ensure the APB/AHB bus
|
|
* transaction is complete before initiating activity on the PPSB
|
|
* block.
|
|
*/
|
|
#define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
|
|
|
|
#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
|
|
|
|
static int __smmu_client_set_hwgrp(struct smmu_client *c,
|
|
unsigned long map, int on)
|
|
{
|
|
int i;
|
|
struct smmu_as *as = c->as;
|
|
u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
|
|
struct smmu_device *smmu = as->smmu;
|
|
|
|
WARN_ON(!on && map);
|
|
if (on && !map)
|
|
return -EINVAL;
|
|
if (!on)
|
|
map = smmu_client_hwgrp(c);
|
|
|
|
for_each_set_bit(i, &map, HWGRP_COUNT) {
|
|
offs = HWGRP_ASID_REG(i);
|
|
val = smmu_read(smmu, offs);
|
|
if (on) {
|
|
if (WARN_ON(val & mask))
|
|
goto err_hw_busy;
|
|
val |= mask;
|
|
} else {
|
|
WARN_ON((val & mask) == mask);
|
|
val &= ~mask;
|
|
}
|
|
smmu_write(smmu, val, offs);
|
|
}
|
|
FLUSH_SMMU_REGS(smmu);
|
|
c->hwgrp = map;
|
|
return 0;
|
|
|
|
err_hw_busy:
|
|
for_each_set_bit(i, &map, HWGRP_COUNT) {
|
|
offs = HWGRP_ASID_REG(i);
|
|
val = smmu_read(smmu, offs);
|
|
val &= ~mask;
|
|
smmu_write(smmu, val, offs);
|
|
}
|
|
return -EBUSY;
|
|
}
|
|
|
|
static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
|
|
{
|
|
u32 val;
|
|
unsigned long flags;
|
|
struct smmu_as *as = c->as;
|
|
struct smmu_device *smmu = as->smmu;
|
|
|
|
spin_lock_irqsave(&smmu->lock, flags);
|
|
val = __smmu_client_set_hwgrp(c, map, on);
|
|
spin_unlock_irqrestore(&smmu->lock, flags);
|
|
return val;
|
|
}
|
|
|
|
/*
|
|
* Flush all TLB entries and all PTC entries
|
|
* Caller must lock smmu
|
|
*/
|
|
static void smmu_flush_regs(struct smmu_device *smmu, int enable)
|
|
{
|
|
u32 val;
|
|
|
|
smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
|
|
SMMU_TLB_FLUSH_ASID_MATCH_disable;
|
|
smmu_write(smmu, val, SMMU_TLB_FLUSH);
|
|
|
|
if (enable)
|
|
smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
}
|
|
|
|
static int smmu_setup_regs(struct smmu_device *smmu)
|
|
{
|
|
int i;
|
|
u32 val;
|
|
|
|
for (i = 0; i < smmu->num_as; i++) {
|
|
struct smmu_as *as = &smmu->as[i];
|
|
struct smmu_client *c;
|
|
|
|
smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
|
|
val = as->pdir_page ?
|
|
SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
|
|
SMMU_PTB_DATA_RESET_VAL;
|
|
smmu_write(smmu, val, SMMU_PTB_DATA);
|
|
|
|
list_for_each_entry(c, &as->client, list)
|
|
__smmu_client_set_hwgrp(c, c->hwgrp, 1);
|
|
}
|
|
|
|
smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
|
|
smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
|
|
smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
|
|
smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
|
|
smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
|
|
smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
|
|
|
|
smmu_flush_regs(smmu, 1);
|
|
|
|
return tegra_ahb_enable_smmu(smmu->ahb);
|
|
}
|
|
|
|
static void flush_ptc_and_tlb(struct smmu_device *smmu,
|
|
struct smmu_as *as, dma_addr_t iova,
|
|
unsigned long *pte, struct page *page, int is_pde)
|
|
{
|
|
u32 val;
|
|
unsigned long tlb_flush_va = is_pde
|
|
? SMMU_TLB_FLUSH_VA(iova, SECTION)
|
|
: SMMU_TLB_FLUSH_VA(iova, GROUP);
|
|
|
|
val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
|
|
smmu_write(smmu, val, SMMU_PTC_FLUSH);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
val = tlb_flush_va |
|
|
SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
|
|
(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
|
|
smmu_write(smmu, val, SMMU_TLB_FLUSH);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
}
|
|
|
|
static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
|
|
{
|
|
unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
|
|
unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
|
|
|
|
if (pdir[pdn] != _PDE_VACANT(pdn)) {
|
|
dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
|
|
|
|
ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
|
|
__free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
|
|
pdir[pdn] = _PDE_VACANT(pdn);
|
|
FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
|
|
flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
|
|
as->pdir_page, 1);
|
|
}
|
|
}
|
|
|
|
static void free_pdir(struct smmu_as *as)
|
|
{
|
|
unsigned addr;
|
|
int count;
|
|
struct device *dev = as->smmu->dev;
|
|
|
|
if (!as->pdir_page)
|
|
return;
|
|
|
|
addr = as->smmu->iovmm_base;
|
|
count = as->smmu->page_count;
|
|
while (count-- > 0) {
|
|
free_ptbl(as, addr);
|
|
addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
|
|
}
|
|
ClearPageReserved(as->pdir_page);
|
|
__free_page(as->pdir_page);
|
|
as->pdir_page = NULL;
|
|
devm_kfree(dev, as->pte_count);
|
|
as->pte_count = NULL;
|
|
}
|
|
|
|
/*
|
|
* Maps PTBL for given iova and returns the PTE address
|
|
* Caller must unmap the mapped PTBL returned in *ptbl_page_p
|
|
*/
|
|
static unsigned long *locate_pte(struct smmu_as *as,
|
|
dma_addr_t iova, bool allocate,
|
|
struct page **ptbl_page_p,
|
|
unsigned int **count)
|
|
{
|
|
unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
|
|
unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
|
|
unsigned long *pdir = page_address(as->pdir_page);
|
|
unsigned long *ptbl;
|
|
|
|
if (pdir[pdn] != _PDE_VACANT(pdn)) {
|
|
/* Mapped entry table already exists */
|
|
*ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
|
|
ptbl = page_address(*ptbl_page_p);
|
|
} else if (!allocate) {
|
|
return NULL;
|
|
} else {
|
|
int pn;
|
|
unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
|
|
|
|
/* Vacant - allocate a new page table */
|
|
dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
|
|
|
|
*ptbl_page_p = alloc_page(GFP_ATOMIC);
|
|
if (!*ptbl_page_p) {
|
|
dev_err(as->smmu->dev,
|
|
"failed to allocate smmu_device page table\n");
|
|
return NULL;
|
|
}
|
|
SetPageReserved(*ptbl_page_p);
|
|
ptbl = (unsigned long *)page_address(*ptbl_page_p);
|
|
for (pn = 0; pn < SMMU_PTBL_COUNT;
|
|
pn++, addr += SMMU_PAGE_SIZE) {
|
|
ptbl[pn] = _PTE_VACANT(addr);
|
|
}
|
|
FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
|
|
pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
|
|
as->pde_attr | _PDE_NEXT);
|
|
FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
|
|
flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
|
|
as->pdir_page, 1);
|
|
}
|
|
*count = &as->pte_count[pdn];
|
|
|
|
return &ptbl[ptn % SMMU_PTBL_COUNT];
|
|
}
|
|
|
|
#ifdef CONFIG_SMMU_SIG_DEBUG
|
|
static void put_signature(struct smmu_as *as,
|
|
dma_addr_t iova, unsigned long pfn)
|
|
{
|
|
struct page *page;
|
|
unsigned long *vaddr;
|
|
|
|
page = pfn_to_page(pfn);
|
|
vaddr = page_address(page);
|
|
if (!vaddr)
|
|
return;
|
|
|
|
vaddr[0] = iova;
|
|
vaddr[1] = pfn << PAGE_SHIFT;
|
|
FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
|
|
}
|
|
#else
|
|
static inline void put_signature(struct smmu_as *as,
|
|
unsigned long addr, unsigned long pfn)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Caller must not hold as->lock
|
|
*/
|
|
static int alloc_pdir(struct smmu_as *as)
|
|
{
|
|
unsigned long *pdir, flags;
|
|
int pdn, err = 0;
|
|
u32 val;
|
|
struct smmu_device *smmu = as->smmu;
|
|
struct page *page;
|
|
unsigned int *cnt;
|
|
|
|
/*
|
|
* do the allocation, then grab as->lock
|
|
*/
|
|
cnt = devm_kzalloc(smmu->dev,
|
|
sizeof(cnt[0]) * SMMU_PDIR_COUNT,
|
|
GFP_KERNEL);
|
|
page = alloc_page(GFP_KERNEL | __GFP_DMA);
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
|
|
if (as->pdir_page) {
|
|
/* We raced, free the redundant */
|
|
err = -EAGAIN;
|
|
goto err_out;
|
|
}
|
|
|
|
if (!page || !cnt) {
|
|
dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
as->pdir_page = page;
|
|
as->pte_count = cnt;
|
|
|
|
SetPageReserved(as->pdir_page);
|
|
pdir = page_address(as->pdir_page);
|
|
|
|
for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
|
|
pdir[pdn] = _PDE_VACANT(pdn);
|
|
FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
|
|
val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
|
|
smmu_write(smmu, val, SMMU_PTC_FLUSH);
|
|
FLUSH_SMMU_REGS(as->smmu);
|
|
val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
|
|
SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
|
|
(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
|
|
smmu_write(smmu, val, SMMU_TLB_FLUSH);
|
|
FLUSH_SMMU_REGS(as->smmu);
|
|
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
devm_kfree(smmu->dev, cnt);
|
|
if (page)
|
|
__free_page(page);
|
|
return err;
|
|
}
|
|
|
|
static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
|
|
{
|
|
unsigned long *pte;
|
|
struct page *page;
|
|
unsigned int *count;
|
|
|
|
pte = locate_pte(as, iova, false, &page, &count);
|
|
if (WARN_ON(!pte))
|
|
return;
|
|
|
|
if (WARN_ON(*pte == _PTE_VACANT(iova)))
|
|
return;
|
|
|
|
*pte = _PTE_VACANT(iova);
|
|
FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
|
|
flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
|
|
if (!--(*count))
|
|
free_ptbl(as, iova);
|
|
}
|
|
|
|
static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
|
|
unsigned long pfn)
|
|
{
|
|
struct smmu_device *smmu = as->smmu;
|
|
unsigned long *pte;
|
|
unsigned int *count;
|
|
struct page *page;
|
|
|
|
pte = locate_pte(as, iova, true, &page, &count);
|
|
if (WARN_ON(!pte))
|
|
return;
|
|
|
|
if (*pte == _PTE_VACANT(iova))
|
|
(*count)++;
|
|
*pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
|
|
if (unlikely((*pte == _PTE_VACANT(iova))))
|
|
(*count)--;
|
|
FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
|
|
flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
|
|
put_signature(as, iova, pfn);
|
|
}
|
|
|
|
static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
|
phys_addr_t pa, size_t bytes, int prot)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
unsigned long pfn = __phys_to_pfn(pa);
|
|
unsigned long flags;
|
|
|
|
dev_dbg(as->smmu->dev, "[%d] %08lx:%pa\n", as->asid, iova, &pa);
|
|
|
|
if (!pfn_valid(pfn))
|
|
return -ENOMEM;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
__smmu_iommu_map_pfn(as, iova, pfn);
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|
size_t bytes)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
unsigned long flags;
|
|
|
|
dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
__smmu_iommu_unmap(as, iova);
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
return SMMU_PAGE_SIZE;
|
|
}
|
|
|
|
static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
unsigned long *pte;
|
|
unsigned int *count;
|
|
struct page *page;
|
|
unsigned long pfn;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
|
|
pte = locate_pte(as, iova, true, &page, &count);
|
|
pfn = *pte & SMMU_PFN_MASK;
|
|
WARN_ON(!pfn_valid(pfn));
|
|
dev_dbg(as->smmu->dev,
|
|
"iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova,
|
|
pfn, as->asid);
|
|
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
return PFN_PHYS(pfn);
|
|
}
|
|
|
|
static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
|
|
unsigned long cap)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int smmu_iommu_attach_dev(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
struct smmu_device *smmu = as->smmu;
|
|
struct smmu_client *client, *c;
|
|
u32 map;
|
|
int err;
|
|
|
|
client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
|
|
if (!client)
|
|
return -ENOMEM;
|
|
client->dev = dev;
|
|
client->as = as;
|
|
map = (unsigned long)dev->platform_data;
|
|
if (!map)
|
|
return -EINVAL;
|
|
|
|
err = smmu_client_enable_hwgrp(client, map);
|
|
if (err)
|
|
goto err_hwgrp;
|
|
|
|
spin_lock(&as->client_lock);
|
|
list_for_each_entry(c, &as->client, list) {
|
|
if (c->dev == dev) {
|
|
dev_err(smmu->dev,
|
|
"%s is already attached\n", dev_name(c->dev));
|
|
err = -EINVAL;
|
|
goto err_client;
|
|
}
|
|
}
|
|
list_add(&client->list, &as->client);
|
|
spin_unlock(&as->client_lock);
|
|
|
|
/*
|
|
* Reserve "page zero" for AVP vectors using a common dummy
|
|
* page.
|
|
*/
|
|
if (map & HWG_AVPC) {
|
|
struct page *page;
|
|
|
|
page = as->smmu->avp_vector_page;
|
|
__smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
|
|
|
|
pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
|
|
}
|
|
|
|
dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
|
|
return 0;
|
|
|
|
err_client:
|
|
smmu_client_disable_hwgrp(client);
|
|
spin_unlock(&as->client_lock);
|
|
err_hwgrp:
|
|
devm_kfree(smmu->dev, client);
|
|
return err;
|
|
}
|
|
|
|
static void smmu_iommu_detach_dev(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
struct smmu_device *smmu = as->smmu;
|
|
struct smmu_client *c;
|
|
|
|
spin_lock(&as->client_lock);
|
|
|
|
list_for_each_entry(c, &as->client, list) {
|
|
if (c->dev == dev) {
|
|
smmu_client_disable_hwgrp(c);
|
|
list_del(&c->list);
|
|
devm_kfree(smmu->dev, c);
|
|
c->as = NULL;
|
|
dev_dbg(smmu->dev,
|
|
"%s is detached\n", dev_name(c->dev));
|
|
goto out;
|
|
}
|
|
}
|
|
dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev));
|
|
out:
|
|
spin_unlock(&as->client_lock);
|
|
}
|
|
|
|
static int smmu_iommu_domain_init(struct iommu_domain *domain)
|
|
{
|
|
int i, err = -EAGAIN;
|
|
unsigned long flags;
|
|
struct smmu_as *as;
|
|
struct smmu_device *smmu = smmu_handle;
|
|
|
|
/* Look for a free AS with lock held */
|
|
for (i = 0; i < smmu->num_as; i++) {
|
|
as = &smmu->as[i];
|
|
|
|
if (as->pdir_page)
|
|
continue;
|
|
|
|
err = alloc_pdir(as);
|
|
if (!err)
|
|
goto found;
|
|
|
|
if (err != -EAGAIN)
|
|
break;
|
|
}
|
|
if (i == smmu->num_as)
|
|
dev_err(smmu->dev, "no free AS\n");
|
|
return err;
|
|
|
|
found:
|
|
spin_lock_irqsave(&smmu->lock, flags);
|
|
|
|
/* Update PDIR register */
|
|
smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
|
|
smmu_write(smmu,
|
|
SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
|
|
spin_unlock_irqrestore(&smmu->lock, flags);
|
|
|
|
domain->priv = as;
|
|
|
|
domain->geometry.aperture_start = smmu->iovmm_base;
|
|
domain->geometry.aperture_end = smmu->iovmm_base +
|
|
smmu->page_count * SMMU_PAGE_SIZE - 1;
|
|
domain->geometry.force_aperture = true;
|
|
|
|
dev_dbg(smmu->dev, "smmu_as@%p\n", as);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
|
|
{
|
|
struct smmu_as *as = domain->priv;
|
|
struct smmu_device *smmu = as->smmu;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
|
|
if (as->pdir_page) {
|
|
spin_lock(&smmu->lock);
|
|
smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
|
|
smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
|
|
FLUSH_SMMU_REGS(smmu);
|
|
spin_unlock(&smmu->lock);
|
|
|
|
free_pdir(as);
|
|
}
|
|
|
|
if (!list_empty(&as->client)) {
|
|
struct smmu_client *c;
|
|
|
|
list_for_each_entry(c, &as->client, list)
|
|
smmu_iommu_detach_dev(domain, c->dev);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
domain->priv = NULL;
|
|
dev_dbg(smmu->dev, "smmu_as@%p\n", as);
|
|
}
|
|
|
|
static const struct iommu_ops smmu_iommu_ops = {
|
|
.domain_init = smmu_iommu_domain_init,
|
|
.domain_destroy = smmu_iommu_domain_destroy,
|
|
.attach_dev = smmu_iommu_attach_dev,
|
|
.detach_dev = smmu_iommu_detach_dev,
|
|
.map = smmu_iommu_map,
|
|
.unmap = smmu_iommu_unmap,
|
|
.iova_to_phys = smmu_iommu_iova_to_phys,
|
|
.domain_has_cap = smmu_iommu_domain_has_cap,
|
|
.pgsize_bitmap = SMMU_IOMMU_PGSIZES,
|
|
};
|
|
|
|
/* Should be in the order of enum */
|
|
static const char * const smmu_debugfs_mc[] = { "mc", };
|
|
static const char * const smmu_debugfs_cache[] = { "tlb", "ptc", };
|
|
|
|
static ssize_t smmu_debugfs_stats_write(struct file *file,
|
|
const char __user *buffer,
|
|
size_t count, loff_t *pos)
|
|
{
|
|
struct smmu_debugfs_info *info;
|
|
struct smmu_device *smmu;
|
|
int i;
|
|
enum {
|
|
_OFF = 0,
|
|
_ON,
|
|
_RESET,
|
|
};
|
|
const char * const command[] = {
|
|
[_OFF] = "off",
|
|
[_ON] = "on",
|
|
[_RESET] = "reset",
|
|
};
|
|
char str[] = "reset";
|
|
u32 val;
|
|
size_t offs;
|
|
|
|
count = min_t(size_t, count, sizeof(str));
|
|
if (copy_from_user(str, buffer, count))
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(command); i++)
|
|
if (strncmp(str, command[i],
|
|
strlen(command[i])) == 0)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(command))
|
|
return -EINVAL;
|
|
|
|
info = file_inode(file)->i_private;
|
|
smmu = info->smmu;
|
|
|
|
offs = SMMU_CACHE_CONFIG(info->cache);
|
|
val = smmu_read(smmu, offs);
|
|
switch (i) {
|
|
case _OFF:
|
|
val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
|
|
val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
|
|
smmu_write(smmu, val, offs);
|
|
break;
|
|
case _ON:
|
|
val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
|
|
val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
|
|
smmu_write(smmu, val, offs);
|
|
break;
|
|
case _RESET:
|
|
val |= SMMU_CACHE_CONFIG_STATS_TEST;
|
|
smmu_write(smmu, val, offs);
|
|
val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
|
|
smmu_write(smmu, val, offs);
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
|
|
val, smmu_read(smmu, offs), offs);
|
|
|
|
return count;
|
|
}
|
|
|
|
static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
|
|
{
|
|
struct smmu_debugfs_info *info = s->private;
|
|
struct smmu_device *smmu = info->smmu;
|
|
int i;
|
|
const char * const stats[] = { "hit", "miss", };
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(stats); i++) {
|
|
u32 val;
|
|
size_t offs;
|
|
|
|
offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
|
|
val = smmu_read(smmu, offs);
|
|
seq_printf(s, "%s:%08x ", stats[i], val);
|
|
|
|
dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
|
|
stats[i], val, offs);
|
|
}
|
|
seq_printf(s, "\n");
|
|
return 0;
|
|
}
|
|
|
|
static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, smmu_debugfs_stats_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations smmu_debugfs_stats_fops = {
|
|
.open = smmu_debugfs_stats_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
.write = smmu_debugfs_stats_write,
|
|
};
|
|
|
|
static void smmu_debugfs_delete(struct smmu_device *smmu)
|
|
{
|
|
debugfs_remove_recursive(smmu->debugfs_root);
|
|
kfree(smmu->debugfs_info);
|
|
}
|
|
|
|
static void smmu_debugfs_create(struct smmu_device *smmu)
|
|
{
|
|
int i;
|
|
size_t bytes;
|
|
struct dentry *root;
|
|
|
|
bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) *
|
|
sizeof(*smmu->debugfs_info);
|
|
smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL);
|
|
if (!smmu->debugfs_info)
|
|
return;
|
|
|
|
root = debugfs_create_dir(dev_name(smmu->dev), NULL);
|
|
if (!root)
|
|
goto err_out;
|
|
smmu->debugfs_root = root;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
|
|
int j;
|
|
struct dentry *mc;
|
|
|
|
mc = debugfs_create_dir(smmu_debugfs_mc[i], root);
|
|
if (!mc)
|
|
goto err_out;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
|
|
struct dentry *cache;
|
|
struct smmu_debugfs_info *info;
|
|
|
|
info = smmu->debugfs_info;
|
|
info += i * ARRAY_SIZE(smmu_debugfs_mc) + j;
|
|
info->smmu = smmu;
|
|
info->mc = i;
|
|
info->cache = j;
|
|
|
|
cache = debugfs_create_file(smmu_debugfs_cache[j],
|
|
S_IWUGO | S_IRUGO, mc,
|
|
(void *)info,
|
|
&smmu_debugfs_stats_fops);
|
|
if (!cache)
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
err_out:
|
|
smmu_debugfs_delete(smmu);
|
|
}
|
|
|
|
static int tegra_smmu_suspend(struct device *dev)
|
|
{
|
|
struct smmu_device *smmu = dev_get_drvdata(dev);
|
|
|
|
smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
|
|
smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
|
|
smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
|
|
smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_smmu_resume(struct device *dev)
|
|
{
|
|
struct smmu_device *smmu = dev_get_drvdata(dev);
|
|
unsigned long flags;
|
|
int err;
|
|
|
|
spin_lock_irqsave(&smmu->lock, flags);
|
|
err = smmu_setup_regs(smmu);
|
|
spin_unlock_irqrestore(&smmu->lock, flags);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_smmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct smmu_device *smmu;
|
|
struct device *dev = &pdev->dev;
|
|
int i, asids, err = 0;
|
|
dma_addr_t uninitialized_var(base);
|
|
size_t bytes, uninitialized_var(size);
|
|
|
|
if (smmu_handle)
|
|
return -EIO;
|
|
|
|
BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
|
|
|
|
if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
|
|
return -ENODEV;
|
|
|
|
bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
|
|
smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
|
|
if (!smmu) {
|
|
dev_err(dev, "failed to allocate smmu_device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
smmu->nregs = pdev->num_resources;
|
|
smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),
|
|
GFP_KERNEL);
|
|
smmu->rege = smmu->regs + smmu->nregs;
|
|
if (!smmu->regs)
|
|
return -ENOMEM;
|
|
for (i = 0; i < smmu->nregs; i++) {
|
|
struct resource *res;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
smmu->regs[i] = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(smmu->regs[i]))
|
|
return PTR_ERR(smmu->regs[i]);
|
|
smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1;
|
|
}
|
|
/* Same as "mc" 1st regiter block start address */
|
|
smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK);
|
|
|
|
err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
|
|
if (err)
|
|
return -ENODEV;
|
|
|
|
if (size & SMMU_PAGE_MASK)
|
|
return -EINVAL;
|
|
|
|
size >>= SMMU_PAGE_SHIFT;
|
|
if (!size)
|
|
return -EINVAL;
|
|
|
|
smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
|
|
if (!smmu->ahb)
|
|
return -ENODEV;
|
|
|
|
smmu->dev = dev;
|
|
smmu->num_as = asids;
|
|
smmu->iovmm_base = base;
|
|
smmu->page_count = size;
|
|
|
|
smmu->translation_enable_0 = ~0;
|
|
smmu->translation_enable_1 = ~0;
|
|
smmu->translation_enable_2 = ~0;
|
|
smmu->asid_security = 0;
|
|
|
|
for (i = 0; i < smmu->num_as; i++) {
|
|
struct smmu_as *as = &smmu->as[i];
|
|
|
|
as->smmu = smmu;
|
|
as->asid = i;
|
|
as->pdir_attr = _PDIR_ATTR;
|
|
as->pde_attr = _PDE_ATTR;
|
|
as->pte_attr = _PTE_ATTR;
|
|
|
|
spin_lock_init(&as->lock);
|
|
spin_lock_init(&as->client_lock);
|
|
INIT_LIST_HEAD(&as->client);
|
|
}
|
|
spin_lock_init(&smmu->lock);
|
|
err = smmu_setup_regs(smmu);
|
|
if (err)
|
|
return err;
|
|
platform_set_drvdata(pdev, smmu);
|
|
|
|
smmu->avp_vector_page = alloc_page(GFP_KERNEL);
|
|
if (!smmu->avp_vector_page)
|
|
return -ENOMEM;
|
|
|
|
smmu_debugfs_create(smmu);
|
|
smmu_handle = smmu;
|
|
bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_smmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct smmu_device *smmu = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
smmu_debugfs_delete(smmu);
|
|
|
|
smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
|
|
for (i = 0; i < smmu->num_as; i++)
|
|
free_pdir(&smmu->as[i]);
|
|
__free_page(smmu->avp_vector_page);
|
|
smmu_handle = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra_smmu_pm_ops = {
|
|
.suspend = tegra_smmu_suspend,
|
|
.resume = tegra_smmu_resume,
|
|
};
|
|
|
|
static struct of_device_id tegra_smmu_of_match[] = {
|
|
{ .compatible = "nvidia,tegra30-smmu", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
|
|
|
|
static struct platform_driver tegra_smmu_driver = {
|
|
.probe = tegra_smmu_probe,
|
|
.remove = tegra_smmu_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "tegra-smmu",
|
|
.pm = &tegra_smmu_pm_ops,
|
|
.of_match_table = tegra_smmu_of_match,
|
|
},
|
|
};
|
|
|
|
static int tegra_smmu_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_smmu_driver);
|
|
}
|
|
|
|
static void __exit tegra_smmu_exit(void)
|
|
{
|
|
platform_driver_unregister(&tegra_smmu_driver);
|
|
}
|
|
|
|
subsys_initcall(tegra_smmu_init);
|
|
module_exit(tegra_smmu_exit);
|
|
|
|
MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
|
|
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
|
|
MODULE_ALIAS("platform:tegra-smmu");
|
|
MODULE_LICENSE("GPL v2");
|