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![Catalin Marinas](/assets/img/avatar_default.png)
GICv3 introduces new system registers accessible with the full msr/mrs syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent binutils understand the new syntax. This patch introduces msr_s/mrs_s assembly macros which generate the equivalent instructions above and converts the existing GICv3 code (both drivers/irqchip/ and arch/arm64/kernel/). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Olof Johansson <olof@lixom.net> Tested-by: Olof Johansson <olof@lixom.net> Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
692 lines
16 KiB
C
692 lines
16 KiB
C
/*
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* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/cputype.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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struct gic_chip_data {
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void __iomem *dist_base;
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void __iomem **redist_base;
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void __percpu __iomem **rdist;
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struct irq_domain *domain;
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u64 redist_stride;
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u32 redist_regions;
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unsigned int irq_nr;
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};
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static struct gic_chip_data gic_data __read_mostly;
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#define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
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#define gic_data_rdist_rd_base() (*gic_data_rdist())
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#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
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/* Our default, arbitrary priority value. Linux only uses one anyway. */
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#define DEFAULT_PMR_VALUE 0xf0
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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static inline int gic_irq_in_rdist(struct irq_data *d)
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{
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return gic_irq(d) < 32;
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}
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
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return gic_data_rdist_sgi_base();
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if (d->hwirq <= 1023) /* SPI -> dist_base */
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return gic_data.dist_base;
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if (d->hwirq >= 8192)
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BUG(); /* LPI Detected!!! */
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return NULL;
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}
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static void gic_do_wait_for_rwp(void __iomem *base)
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{
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u32 count = 1000000; /* 1s! */
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while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
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count--;
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if (!count) {
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pr_err_ratelimited("RWP timeout, gone fishing\n");
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return;
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}
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cpu_relax();
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udelay(1);
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};
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}
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/* Wait for completion of a distributor change */
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static void gic_dist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data.dist_base);
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}
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/* Wait for completion of a redistributor change */
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static void gic_redist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data_rdist_rd_base());
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}
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/* Low level accessors */
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static u64 gic_read_iar(void)
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{
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u64 irqstat;
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asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
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return irqstat;
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}
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static void gic_write_pmr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
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}
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static void gic_write_ctlr(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
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isb();
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}
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static void gic_write_grpen1(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
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isb();
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}
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static void gic_write_sgi1r(u64 val)
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{
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asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
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}
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static void gic_enable_sre(void)
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{
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u64 val;
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asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
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val |= ICC_SRE_EL1_SRE;
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asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
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isb();
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/*
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* Need to check that the SRE bit has actually been set. If
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* not, it means that SRE is disabled at EL2. We're going to
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* die painfully, and there is nothing we can do about it.
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*
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* Kindly inform the luser.
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*/
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asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
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if (!(val & ICC_SRE_EL1_SRE))
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pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
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}
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static void gic_enable_redist(void)
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{
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void __iomem *rbase;
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u32 count = 1000000; /* 1s! */
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u32 val;
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rbase = gic_data_rdist_rd_base();
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/* Wake up this CPU redistributor */
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val = readl_relaxed(rbase + GICR_WAKER);
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val &= ~GICR_WAKER_ProcessorSleep;
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writel_relaxed(val, rbase + GICR_WAKER);
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while (readl_relaxed(rbase + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) {
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count--;
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if (!count) {
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pr_err_ratelimited("redist didn't wake up...\n");
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return;
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}
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cpu_relax();
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udelay(1);
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};
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}
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/*
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* Routines to disable, enable, EOI and route interrupts
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*/
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void (*rwp_wait)(void);
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void __iomem *base;
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if (gic_irq_in_rdist(d)) {
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base = gic_data_rdist_sgi_base();
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rwp_wait = gic_redist_wait_for_rwp;
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} else {
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base = gic_data.dist_base;
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rwp_wait = gic_dist_wait_for_rwp;
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}
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writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
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rwp_wait();
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}
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void __iomem *base;
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GICD_ICENABLER);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GICD_ISENABLER);
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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gic_write_eoir(gic_irq(d));
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq = gic_irq(d);
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void (*rwp_wait)(void);
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void __iomem *base;
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/* Interrupt configuration for SGIs can't be changed */
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if (irq < 16)
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return -EINVAL;
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if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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if (gic_irq_in_rdist(d)) {
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base = gic_data_rdist_sgi_base();
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rwp_wait = gic_redist_wait_for_rwp;
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} else {
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base = gic_data.dist_base;
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rwp_wait = gic_dist_wait_for_rwp;
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}
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gic_configure_irq(irq, type, base, rwp_wait);
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return 0;
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}
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static u64 gic_mpidr_to_affinity(u64 mpidr)
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{
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u64 aff;
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aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
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MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 0));
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return aff;
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}
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static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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{
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u64 irqnr;
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do {
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irqnr = gic_read_iar();
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if (likely(irqnr > 15 && irqnr < 1020)) {
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u64 irq = irq_find_mapping(gic_data.domain, irqnr);
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if (likely(irq)) {
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handle_IRQ(irq, regs);
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continue;
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}
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WARN_ONCE(true, "Unexpected SPI received!\n");
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gic_write_eoir(irqnr);
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}
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if (irqnr < 16) {
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gic_write_eoir(irqnr);
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#ifdef CONFIG_SMP
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handle_IPI(irqnr, regs);
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#else
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WARN_ONCE(true, "Unexpected SGI received!\n");
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#endif
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continue;
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}
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} while (irqnr != ICC_IAR1_EL1_SPURIOUS);
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}
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static void __init gic_dist_init(void)
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{
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unsigned int i;
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u64 affinity;
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void __iomem *base = gic_data.dist_base;
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/* Disable the distributor */
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writel_relaxed(0, base + GICD_CTLR);
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gic_dist_wait_for_rwp();
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gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
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/* Enable distributor with ARE, Group1 */
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writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
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base + GICD_CTLR);
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/*
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* Set all global interrupts to the boot CPU only. ARE must be
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* enabled.
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*/
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affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
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for (i = 32; i < gic_data.irq_nr; i++)
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writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
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}
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static int gic_populate_rdist(void)
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{
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u64 mpidr = cpu_logical_map(smp_processor_id());
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u64 typer;
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u32 aff;
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int i;
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/*
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* Convert affinity to a 32bit value that can be matched to
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* GICR_TYPER bits [63:32].
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*/
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aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
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MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 0));
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for (i = 0; i < gic_data.redist_regions; i++) {
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void __iomem *ptr = gic_data.redist_base[i];
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u32 reg;
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reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
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if (reg != GIC_PIDR2_ARCH_GICv3 &&
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reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
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pr_warn("No redistributor present @%p\n", ptr);
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break;
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}
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do {
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typer = readq_relaxed(ptr + GICR_TYPER);
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if ((typer >> 32) == aff) {
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gic_data_rdist_rd_base() = ptr;
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pr_info("CPU%d: found redistributor %llx @%p\n",
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smp_processor_id(),
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(unsigned long long)mpidr, ptr);
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return 0;
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}
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if (gic_data.redist_stride) {
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ptr += gic_data.redist_stride;
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} else {
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ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
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if (typer & GICR_TYPER_VLPIS)
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ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
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}
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} while (!(typer & GICR_TYPER_LAST));
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}
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/* We couldn't even deal with ourselves... */
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WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
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smp_processor_id(), (unsigned long long)mpidr);
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return -ENODEV;
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}
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static void gic_cpu_init(void)
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{
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void __iomem *rbase;
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/* Register ourselves with the rest of the world */
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if (gic_populate_rdist())
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return;
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gic_enable_redist();
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rbase = gic_data_rdist_sgi_base();
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gic_cpu_config(rbase, gic_redist_wait_for_rwp);
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/* Enable system registers */
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gic_enable_sre();
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/* Set priority mask register */
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gic_write_pmr(DEFAULT_PMR_VALUE);
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/* EOI deactivates interrupt too (mode 0) */
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gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
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/* ... and let's hit the road... */
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gic_write_grpen1(1);
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}
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#ifdef CONFIG_SMP
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static int gic_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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gic_cpu_init();
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return NOTIFY_OK;
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}
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/*
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* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
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* priority because the GIC needs to be up before the ARM generic timers.
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*/
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static struct notifier_block gic_cpu_notifier = {
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.notifier_call = gic_secondary_init,
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.priority = 100,
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};
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static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
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u64 cluster_id)
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{
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int cpu = *base_cpu;
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u64 mpidr = cpu_logical_map(cpu);
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u16 tlist = 0;
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while (cpu < nr_cpu_ids) {
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/*
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* If we ever get a cluster of more than 16 CPUs, just
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* scream and skip that CPU.
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*/
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if (WARN_ON((mpidr & 0xff) >= 16))
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goto out;
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tlist |= 1 << (mpidr & 0xf);
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cpu = cpumask_next(cpu, mask);
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if (cpu == nr_cpu_ids)
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goto out;
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mpidr = cpu_logical_map(cpu);
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if (cluster_id != (mpidr & ~0xffUL)) {
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cpu--;
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goto out;
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}
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}
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out:
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*base_cpu = cpu;
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return tlist;
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}
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static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
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{
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u64 val;
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val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
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MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
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irq << 24 |
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MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
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tlist);
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pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
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gic_write_sgi1r(val);
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}
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static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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if (WARN_ON(irq >= 16))
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return;
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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smp_wmb();
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for_each_cpu_mask(cpu, *mask) {
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u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
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u16 tlist;
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tlist = gic_compute_target_list(&cpu, mask, cluster_id);
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gic_send_sgi(cluster_id, tlist, irq);
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}
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/* Force the above writes to ICC_SGI1R_EL1 to be executed */
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isb();
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}
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|
|
static void gic_smp_init(void)
|
|
{
|
|
set_smp_cross_call(gic_raise_softirq);
|
|
register_cpu_notifier(&gic_cpu_notifier);
|
|
}
|
|
|
|
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
|
bool force)
|
|
{
|
|
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
|
void __iomem *reg;
|
|
int enabled;
|
|
u64 val;
|
|
|
|
if (gic_irq_in_rdist(d))
|
|
return -EINVAL;
|
|
|
|
/* If interrupt was enabled, disable it first */
|
|
enabled = gic_peek_irq(d, GICD_ISENABLER);
|
|
if (enabled)
|
|
gic_mask_irq(d);
|
|
|
|
reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
|
|
val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
|
|
|
|
writeq_relaxed(val, reg);
|
|
|
|
/*
|
|
* If the interrupt was enabled, enabled it again. Otherwise,
|
|
* just wait for the distributor to have digested our changes.
|
|
*/
|
|
if (enabled)
|
|
gic_unmask_irq(d);
|
|
else
|
|
gic_dist_wait_for_rwp();
|
|
|
|
return IRQ_SET_MASK_OK;
|
|
}
|
|
#else
|
|
#define gic_set_affinity NULL
|
|
#define gic_smp_init() do { } while(0)
|
|
#endif
|
|
|
|
static struct irq_chip gic_chip = {
|
|
.name = "GICv3",
|
|
.irq_mask = gic_mask_irq,
|
|
.irq_unmask = gic_unmask_irq,
|
|
.irq_eoi = gic_eoi_irq,
|
|
.irq_set_type = gic_set_type,
|
|
.irq_set_affinity = gic_set_affinity,
|
|
};
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
/* SGIs are private to the core kernel */
|
|
if (hw < 16)
|
|
return -EPERM;
|
|
/* PPIs */
|
|
if (hw < 32) {
|
|
irq_set_percpu_devid(irq);
|
|
irq_set_chip_and_handler(irq, &gic_chip,
|
|
handle_percpu_devid_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
|
}
|
|
/* SPIs */
|
|
if (hw >= 32 && hw < gic_data.irq_nr) {
|
|
irq_set_chip_and_handler(irq, &gic_chip,
|
|
handle_fasteoi_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
irq_set_chip_data(irq, d->host_data);
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_xlate(struct irq_domain *d,
|
|
struct device_node *controller,
|
|
const u32 *intspec, unsigned int intsize,
|
|
unsigned long *out_hwirq, unsigned int *out_type)
|
|
{
|
|
if (d->of_node != controller)
|
|
return -EINVAL;
|
|
if (intsize < 3)
|
|
return -EINVAL;
|
|
|
|
switch(intspec[0]) {
|
|
case 0: /* SPI */
|
|
*out_hwirq = intspec[1] + 32;
|
|
break;
|
|
case 1: /* PPI */
|
|
*out_hwirq = intspec[1] + 16;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.map = gic_irq_domain_map,
|
|
.xlate = gic_irq_domain_xlate,
|
|
};
|
|
|
|
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
|
{
|
|
void __iomem *dist_base;
|
|
void __iomem **redist_base;
|
|
u64 redist_stride;
|
|
u32 redist_regions;
|
|
u32 reg;
|
|
int gic_irqs;
|
|
int err;
|
|
int i;
|
|
|
|
dist_base = of_iomap(node, 0);
|
|
if (!dist_base) {
|
|
pr_err("%s: unable to map gic dist registers\n",
|
|
node->full_name);
|
|
return -ENXIO;
|
|
}
|
|
|
|
reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
|
if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
|
|
pr_err("%s: no distributor detected, giving up\n",
|
|
node->full_name);
|
|
err = -ENODEV;
|
|
goto out_unmap_dist;
|
|
}
|
|
|
|
if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
|
|
redist_regions = 1;
|
|
|
|
redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
|
|
if (!redist_base) {
|
|
err = -ENOMEM;
|
|
goto out_unmap_dist;
|
|
}
|
|
|
|
for (i = 0; i < redist_regions; i++) {
|
|
redist_base[i] = of_iomap(node, 1 + i);
|
|
if (!redist_base[i]) {
|
|
pr_err("%s: couldn't map region %d\n",
|
|
node->full_name, i);
|
|
err = -ENODEV;
|
|
goto out_unmap_rdist;
|
|
}
|
|
}
|
|
|
|
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
|
|
redist_stride = 0;
|
|
|
|
gic_data.dist_base = dist_base;
|
|
gic_data.redist_base = redist_base;
|
|
gic_data.redist_regions = redist_regions;
|
|
gic_data.redist_stride = redist_stride;
|
|
|
|
/*
|
|
* Find out how many interrupts are supported.
|
|
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
|
*/
|
|
gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
|
|
gic_irqs = (gic_irqs + 1) * 32;
|
|
if (gic_irqs > 1020)
|
|
gic_irqs = 1020;
|
|
gic_data.irq_nr = gic_irqs;
|
|
|
|
gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
|
|
&gic_data);
|
|
gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
|
|
|
|
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
|
|
err = -ENOMEM;
|
|
goto out_free;
|
|
}
|
|
|
|
set_handle_irq(gic_handle_irq);
|
|
|
|
gic_smp_init();
|
|
gic_dist_init();
|
|
gic_cpu_init();
|
|
|
|
return 0;
|
|
|
|
out_free:
|
|
if (gic_data.domain)
|
|
irq_domain_remove(gic_data.domain);
|
|
free_percpu(gic_data.rdist);
|
|
out_unmap_rdist:
|
|
for (i = 0; i < redist_regions; i++)
|
|
if (redist_base[i])
|
|
iounmap(redist_base[i]);
|
|
kfree(redist_base);
|
|
out_unmap_dist:
|
|
iounmap(dist_base);
|
|
return err;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
|