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drivers/parisc/iommu-helpers.h:62: error: implicit declaration of function 'prefetchw' make[3]: *** [drivers/parisc/sba_iommu.o] Error 1 drivers/parisc/iommu-helpers.h needs to #include <linux/prefetch.h> where prefetchw is declared. Signed-off-by: WANG Cong <xiyou.wangcong@gmail.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
#include <linux/prefetch.h>
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/**
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* iommu_fill_pdir - Insert coalesced scatter/gather chunks into the I/O Pdir.
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* @ioc: The I/O Controller.
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* @startsg: The scatter/gather list of coalesced chunks.
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* @nents: The number of entries in the scatter/gather list.
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* @hint: The DMA Hint.
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*
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* This function inserts the coalesced scatter/gather list chunks into the
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* I/O Controller's I/O Pdir.
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*/
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static inline unsigned int
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iommu_fill_pdir(struct ioc *ioc, struct scatterlist *startsg, int nents,
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unsigned long hint,
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void (*iommu_io_pdir_entry)(u64 *, space_t, unsigned long,
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unsigned long))
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{
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struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
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unsigned int n_mappings = 0;
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unsigned long dma_offset = 0, dma_len = 0;
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u64 *pdirp = NULL;
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/* Horrible hack. For efficiency's sake, dma_sg starts one
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* entry below the true start (it is immediately incremented
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* in the loop) */
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dma_sg--;
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while (nents-- > 0) {
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unsigned long vaddr;
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long size;
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DBG_RUN_SG(" %d : %08lx/%05x %08lx/%05x\n", nents,
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(unsigned long)sg_dma_address(startsg), cnt,
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sg_virt_addr(startsg), startsg->length
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);
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/*
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** Look for the start of a new DMA stream
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*/
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if (sg_dma_address(startsg) & PIDE_FLAG) {
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u32 pide = sg_dma_address(startsg) & ~PIDE_FLAG;
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BUG_ON(pdirp && (dma_len != sg_dma_len(dma_sg)));
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dma_sg++;
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dma_len = sg_dma_len(startsg);
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sg_dma_len(startsg) = 0;
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dma_offset = (unsigned long) pide & ~IOVP_MASK;
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n_mappings++;
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#if defined(ZX1_SUPPORT)
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/* Pluto IOMMU IO Virt Address is not zero based */
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sg_dma_address(dma_sg) = pide | ioc->ibase;
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#else
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/* SBA, ccio, and dino are zero based.
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* Trying to save a few CPU cycles for most users.
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*/
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sg_dma_address(dma_sg) = pide;
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#endif
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pdirp = &(ioc->pdir_base[pide >> IOVP_SHIFT]);
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prefetchw(pdirp);
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}
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BUG_ON(pdirp == NULL);
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vaddr = sg_virt_addr(startsg);
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sg_dma_len(dma_sg) += startsg->length;
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size = startsg->length + dma_offset;
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dma_offset = 0;
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#ifdef IOMMU_MAP_STATS
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ioc->msg_pages += startsg->length >> IOVP_SHIFT;
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#endif
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do {
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iommu_io_pdir_entry(pdirp, KERNEL_SPACE,
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vaddr, hint);
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vaddr += IOVP_SIZE;
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size -= IOVP_SIZE;
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pdirp++;
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} while(unlikely(size > 0));
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startsg++;
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}
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return(n_mappings);
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}
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/*
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** First pass is to walk the SG list and determine where the breaks are
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** in the DMA stream. Allocates PDIR entries but does not fill them.
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** Returns the number of DMA chunks.
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**
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** Doing the fill separate from the coalescing/allocation keeps the
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** code simpler. Future enhancement could make one pass through
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** the sglist do both.
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*/
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static inline unsigned int
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iommu_coalesce_chunks(struct ioc *ioc, struct device *dev,
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struct scatterlist *startsg, int nents,
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int (*iommu_alloc_range)(struct ioc *, struct device *, size_t))
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{
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struct scatterlist *contig_sg; /* contig chunk head */
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unsigned long dma_offset, dma_len; /* start/len of DMA stream */
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unsigned int n_mappings = 0;
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unsigned int max_seg_size = dma_get_max_seg_size(dev);
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while (nents > 0) {
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/*
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** Prepare for first/next DMA stream
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*/
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contig_sg = startsg;
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dma_len = startsg->length;
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dma_offset = sg_virt_addr(startsg) & ~IOVP_MASK;
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/* PARANOID: clear entries */
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sg_dma_address(startsg) = 0;
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sg_dma_len(startsg) = 0;
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/*
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** This loop terminates one iteration "early" since
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** it's always looking one "ahead".
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*/
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while(--nents > 0) {
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unsigned long prevstartsg_end, startsg_end;
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prevstartsg_end = sg_virt_addr(startsg) +
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startsg->length;
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startsg++;
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startsg_end = sg_virt_addr(startsg) +
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startsg->length;
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/* PARANOID: clear entries */
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sg_dma_address(startsg) = 0;
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sg_dma_len(startsg) = 0;
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/*
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** First make sure current dma stream won't
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** exceed DMA_CHUNK_SIZE if we coalesce the
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** next entry.
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*/
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if(unlikely(ALIGN(dma_len + dma_offset + startsg->length,
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IOVP_SIZE) > DMA_CHUNK_SIZE))
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break;
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if (startsg->length + dma_len > max_seg_size)
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break;
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/*
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** Next see if we can append the next chunk (i.e.
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** it must end on one page and begin on another
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*/
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if (unlikely(((prevstartsg_end | sg_virt_addr(startsg)) & ~PAGE_MASK) != 0))
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break;
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dma_len += startsg->length;
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}
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/*
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** End of DMA Stream
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** Terminate last VCONTIG block.
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** Allocate space for DMA stream.
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*/
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sg_dma_len(contig_sg) = dma_len;
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dma_len = ALIGN(dma_len + dma_offset, IOVP_SIZE);
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sg_dma_address(contig_sg) =
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PIDE_FLAG
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| (iommu_alloc_range(ioc, dev, dma_len) << IOVP_SHIFT)
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| dma_offset;
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n_mappings++;
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}
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return n_mappings;
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}
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