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ae85b23c65
pci_get_legacy_ide_irq() is only used on platforms that support PNP, so many architectures define it but never use it. Replace uses of it with ATA_PRIMARY_IRQ() and ATA_SECONDARY_IRQ(), which provide the same functionality. Since pci_get_legacy_ide_irq() is no longer used, remove all the architecture-specific definitions of it as well as asm-generic/pci.h, which only provides pci_get_legacy_ide_irq() [bhelgaas: commit log] Co-developed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20220722214944.831438-2-shorne@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Pierre Morel <pmorel@linux.ibm.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_PCI_H
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#define __ASM_SH_PCI_H
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/* Can be used to override the logic in pci_scan_bus for skipping
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already-configured bus numbers - to be used for buggy BIOSes
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or architectures with incomplete PCI setup by the loader */
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#define pcibios_assign_all_busses() 1
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/*
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* A board can define one or more PCI channels that represent built-in (or
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* external) PCI controllers.
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*/
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struct pci_channel {
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struct pci_channel *next;
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struct pci_bus *bus;
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struct pci_ops *pci_ops;
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struct resource *resources;
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unsigned int nr_resources;
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unsigned long io_offset;
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unsigned long mem_offset;
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unsigned long reg_base;
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unsigned long io_map_base;
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unsigned int index;
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unsigned int need_domain_info;
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/* Optional error handling */
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struct timer_list err_timer, serr_timer;
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unsigned int err_irq, serr_irq;
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};
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/* arch/sh/drivers/pci/pci.c */
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extern raw_spinlock_t pci_config_lock;
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extern int register_pci_controller(struct pci_channel *hose);
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extern void pcibios_report_status(unsigned int status_mask, int warn);
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/* arch/sh/drivers/pci/common.c */
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extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u8 *value);
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extern int early_read_config_word(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u16 *value);
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extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u32 *value);
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extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u8 value);
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extern int early_write_config_word(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u16 value);
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extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
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int bus, int devfn, int offset, u32 value);
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extern void pcibios_enable_timers(struct pci_channel *hose);
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extern unsigned int pcibios_handle_status_errors(unsigned long addr,
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unsigned int status, struct pci_channel *hose);
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extern int pci_is_66mhz_capable(struct pci_channel *hose,
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int top_bus, int current_bus);
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extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
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#define HAVE_PCI_MMAP
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#define ARCH_GENERIC_PCI_MMAP_RESOURCE
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/* Dynamic DMA mapping stuff.
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* SuperH has everything mapped statically like x86.
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*/
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#ifdef CONFIG_PCI
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/*
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* None of the SH PCI controllers support MWI, it is always treated as a
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* direct memory write.
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*/
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#define PCI_DISABLE_MWI
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#endif
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/* Board-specific fixup routines. */
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int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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struct pci_channel *hose = bus->sysdata;
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return hose->need_domain_info;
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}
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#endif /* __ASM_SH_PCI_H */
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