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![Stephen Boyd](/assets/img/avatar_default.png)
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
255 lines
6.8 KiB
C
255 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "berlin2-div.h"
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/*
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* Clock dividers in Berlin2 SoCs comprise a complex cell to select
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* input pll and divider. The virtual structure as it is used in Marvell
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* BSP code can be seen as:
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*
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* +---+
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* pll0 --------------->| 0 | +---+
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* +---+ |(B)|--+--------------->| 0 | +---+
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* pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
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* pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|->
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* ... -->|(A)|--+ | +--------+ +---+ +-->| 1 | +---+
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* ... -->| | +-->|(D) 1:3 |----------+ +---+
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* pll1.N -->| N | +---------
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* +---+
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*
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* (A) input pll clock mux controlled by <PllSelect[1:n]>
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* (B) input pll bypass mux controlled by <PllSwitch>
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* (C) programmable clock divider controlled by <Select[1:n]>
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* (D) constant div-by-3 clock divider
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* (E) programmable clock divider bypass controlled by <Switch>
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* (F) constant div-by-3 clock mux controlled by <D3Switch>
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* (G) clock gate controlled by <Enable>
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*
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* For whatever reason, above control signals come in two flavors:
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* - single register dividers with all bits in one register
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* - shared register dividers with bits spread over multiple registers
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* (including signals for the same cell spread over consecutive registers)
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*
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* Also, clock gate and pll mux is not available on every div cell, so
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* we have to deal with those, too. We reuse common clock composite driver
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* for it.
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*/
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#define PLL_SELECT_MASK 0x7
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#define DIV_SELECT_MASK 0x7
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struct berlin2_div {
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struct clk_hw hw;
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void __iomem *base;
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struct berlin2_div_map map;
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spinlock_t *lock;
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};
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#define to_berlin2_div(hw) container_of(hw, struct berlin2_div, hw)
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static u8 clk_div[] = { 1, 2, 4, 6, 8, 12, 1, 1 };
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static int berlin2_div_is_enabled(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg >>= map->gate_shift;
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if (div->lock)
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spin_unlock(div->lock);
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return (reg & 0x1);
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}
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static int berlin2_div_enable(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg |= BIT(map->gate_shift);
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writel_relaxed(reg, div->base + map->gate_offs);
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if (div->lock)
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spin_unlock(div->lock);
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return 0;
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}
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static void berlin2_div_disable(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg &= ~BIT(map->gate_shift);
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writel_relaxed(reg, div->base + map->gate_offs);
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if (div->lock)
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spin_unlock(div->lock);
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}
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static int berlin2_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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/* index == 0 is PLL_SWITCH */
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reg = readl_relaxed(div->base + map->pll_switch_offs);
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if (index == 0)
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reg &= ~BIT(map->pll_switch_shift);
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else
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reg |= BIT(map->pll_switch_shift);
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writel_relaxed(reg, div->base + map->pll_switch_offs);
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/* index > 0 is PLL_SELECT */
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if (index > 0) {
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reg = readl_relaxed(div->base + map->pll_select_offs);
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reg &= ~(PLL_SELECT_MASK << map->pll_select_shift);
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reg |= (index - 1) << map->pll_select_shift;
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writel_relaxed(reg, div->base + map->pll_select_offs);
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}
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if (div->lock)
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spin_unlock(div->lock);
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return 0;
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}
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static u8 berlin2_div_get_parent(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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u8 index = 0;
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if (div->lock)
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spin_lock(div->lock);
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/* PLL_SWITCH == 0 is index 0 */
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reg = readl_relaxed(div->base + map->pll_switch_offs);
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reg &= BIT(map->pll_switch_shift);
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if (reg) {
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reg = readl_relaxed(div->base + map->pll_select_offs);
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reg >>= map->pll_select_shift;
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reg &= PLL_SELECT_MASK;
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index = 1 + reg;
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}
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if (div->lock)
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spin_unlock(div->lock);
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return index;
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}
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static unsigned long berlin2_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 divsw, div3sw, divider = 1;
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if (div->lock)
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spin_lock(div->lock);
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divsw = readl_relaxed(div->base + map->div_switch_offs) &
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(1 << map->div_switch_shift);
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div3sw = readl_relaxed(div->base + map->div3_switch_offs) &
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(1 << map->div3_switch_shift);
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/* constant divide-by-3 (dominant) */
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if (div3sw != 0) {
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divider = 3;
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/* divider can be bypassed with DIV_SWITCH == 0 */
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} else if (divsw == 0) {
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divider = 1;
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/* clock divider determined by DIV_SELECT */
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} else {
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u32 reg;
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reg = readl_relaxed(div->base + map->div_select_offs);
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reg >>= map->div_select_shift;
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reg &= DIV_SELECT_MASK;
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divider = clk_div[reg];
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}
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if (div->lock)
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spin_unlock(div->lock);
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return parent_rate / divider;
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}
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static const struct clk_ops berlin2_div_rate_ops = {
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.recalc_rate = berlin2_div_recalc_rate,
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};
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static const struct clk_ops berlin2_div_gate_ops = {
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.is_enabled = berlin2_div_is_enabled,
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.enable = berlin2_div_enable,
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.disable = berlin2_div_disable,
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};
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static const struct clk_ops berlin2_div_mux_ops = {
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.set_parent = berlin2_div_set_parent,
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.get_parent = berlin2_div_get_parent,
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};
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struct clk_hw * __init
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berlin2_div_register(const struct berlin2_div_map *map,
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void __iomem *base, const char *name, u8 div_flags,
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const char **parent_names, int num_parents,
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unsigned long flags, spinlock_t *lock)
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{
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const struct clk_ops *mux_ops = &berlin2_div_mux_ops;
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const struct clk_ops *rate_ops = &berlin2_div_rate_ops;
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const struct clk_ops *gate_ops = &berlin2_div_gate_ops;
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struct berlin2_div *div;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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/* copy div_map to allow __initconst */
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memcpy(&div->map, map, sizeof(*map));
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div->base = base;
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div->lock = lock;
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if ((div_flags & BERLIN2_DIV_HAS_GATE) == 0)
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gate_ops = NULL;
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if ((div_flags & BERLIN2_DIV_HAS_MUX) == 0)
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mux_ops = NULL;
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return clk_hw_register_composite(NULL, name, parent_names, num_parents,
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&div->hw, mux_ops, &div->hw, rate_ops,
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&div->hw, gate_ops, flags);
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}
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