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7b2e1de8ae
Add MT8195 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-12-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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static const struct mtk_gate_regs ccu_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_CCU(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate ccu_clks[] = {
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GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0),
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GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
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GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
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GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3),
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};
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static const struct mtk_clk_desc ccu_desc = {
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.clks = ccu_clks,
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.num_clks = ARRAY_SIZE(ccu_clks),
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};
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static const struct of_device_id of_match_clk_mt8195_ccu[] = {
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{
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.compatible = "mediatek,mt8195-ccusys",
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.data = &ccu_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8195_ccu_drv = {
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.probe = mtk_clk_simple_probe,
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.driver = {
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.name = "clk-mt8195-ccu",
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.of_match_table = of_match_clk_mt8195_ccu,
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},
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};
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builtin_platform_driver(clk_mt8195_ccu_drv);
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