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![Jerome Brunet](/assets/img/avatar_default.png)
This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
186 lines
5.2 KiB
C
186 lines
5.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include "clk-regmap.h"
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#include "clk-phase.h"
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#define phase_step(_width) (360 / (1 << (_width)))
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static inline struct meson_clk_phase_data *
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meson_clk_phase_data(struct clk_regmap *clk)
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{
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return (struct meson_clk_phase_data *)clk->data;
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}
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static int meson_clk_degrees_from_val(unsigned int val, unsigned int width)
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{
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return phase_step(width) * val;
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}
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static unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width)
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{
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unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width));
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/*
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* This last calculation is here for cases when degrees is rounded
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* to 360, in which case val == (1 << width).
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*/
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return val % (1 << width);
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}
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static int meson_clk_phase_get_phase(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
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unsigned int val;
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val = meson_parm_read(clk->map, &phase->ph);
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return meson_clk_degrees_from_val(val, phase->ph.width);
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}
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static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
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unsigned int val;
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val = meson_clk_degrees_to_val(degrees, phase->ph.width);
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meson_parm_write(clk->map, &phase->ph, val);
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return 0;
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}
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const struct clk_ops meson_clk_phase_ops = {
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.get_phase = meson_clk_phase_get_phase,
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.set_phase = meson_clk_phase_set_phase,
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};
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EXPORT_SYMBOL_GPL(meson_clk_phase_ops);
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/*
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* This is a special clock for the audio controller.
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* The phase of mst_sclk clock output can be controlled independently
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* for the outside world (ph0), the tdmout (ph1) and tdmin (ph2).
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* Controlling these 3 phases as just one makes things simpler and
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* give the same clock view to all the element on the i2s bus.
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* If necessary, we can still control the phase in the tdm block
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* which makes these independent control redundant.
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*/
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static inline struct meson_clk_triphase_data *
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meson_clk_triphase_data(struct clk_regmap *clk)
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{
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return (struct meson_clk_triphase_data *)clk->data;
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}
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static int meson_clk_triphase_sync(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
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unsigned int val;
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/* Get phase 0 and sync it to phase 1 and 2 */
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val = meson_parm_read(clk->map, &tph->ph0);
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meson_parm_write(clk->map, &tph->ph1, val);
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meson_parm_write(clk->map, &tph->ph2, val);
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return 0;
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}
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static int meson_clk_triphase_get_phase(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
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unsigned int val;
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/* Phase are in sync, reading phase 0 is enough */
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val = meson_parm_read(clk->map, &tph->ph0);
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return meson_clk_degrees_from_val(val, tph->ph0.width);
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}
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static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
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unsigned int val;
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val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
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meson_parm_write(clk->map, &tph->ph0, val);
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meson_parm_write(clk->map, &tph->ph1, val);
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meson_parm_write(clk->map, &tph->ph2, val);
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return 0;
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}
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const struct clk_ops meson_clk_triphase_ops = {
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.init = meson_clk_triphase_sync,
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.get_phase = meson_clk_triphase_get_phase,
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.set_phase = meson_clk_triphase_set_phase,
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};
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EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
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/*
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* This is a special clock for the audio controller.
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* This drive a bit clock inverter for which the
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* opposite value of the inverter bit needs to be manually
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* set into another bit
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*/
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static inline struct meson_sclk_ws_inv_data *
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meson_sclk_ws_inv_data(struct clk_regmap *clk)
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{
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return (struct meson_sclk_ws_inv_data *)clk->data;
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}
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static int meson_sclk_ws_inv_sync(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
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unsigned int val;
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/* Get phase and sync the inverted value to ws */
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val = meson_parm_read(clk->map, &tph->ph);
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meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
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return 0;
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}
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static int meson_sclk_ws_inv_get_phase(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
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unsigned int val;
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val = meson_parm_read(clk->map, &tph->ph);
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return meson_clk_degrees_from_val(val, tph->ph.width);
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}
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static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
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unsigned int val;
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val = meson_clk_degrees_to_val(degrees, tph->ph.width);
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meson_parm_write(clk->map, &tph->ph, val);
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meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
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return 0;
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}
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const struct clk_ops meson_sclk_ws_inv_ops = {
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.init = meson_sclk_ws_inv_sync,
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.get_phase = meson_sclk_ws_inv_get_phase,
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.set_phase = meson_sclk_ws_inv_set_phase,
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};
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EXPORT_SYMBOL_GPL(meson_sclk_ws_inv_ops);
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MODULE_DESCRIPTION("Amlogic phase driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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