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![Jerome Brunet](/assets/img/avatar_default.png)
This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
32 lines
638 B
C
32 lines
638 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLK_PHASE_H
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#define __MESON_CLK_PHASE_H
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#include <linux/clk-provider.h>
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#include "parm.h"
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struct meson_clk_phase_data {
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struct parm ph;
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};
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struct meson_clk_triphase_data {
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struct parm ph0;
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struct parm ph1;
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struct parm ph2;
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};
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struct meson_sclk_ws_inv_data {
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struct parm ph;
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struct parm ws;
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};
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extern const struct clk_ops meson_clk_phase_ops;
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extern const struct clk_ops meson_clk_triphase_ops;
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extern const struct clk_ops meson_sclk_ws_inv_ops;
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#endif /* __MESON_CLK_PHASE_H */
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