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![Martin Blumenstingl](/assets/img/avatar_default.png)
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
186 lines
5 KiB
C
186 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/module.h>
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#include "clk-regmap.h"
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static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
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int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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set ^= enable;
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return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx),
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set ? BIT(gate->bit_idx) : 0);
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}
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static int clk_regmap_gate_enable(struct clk_hw *hw)
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{
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return clk_regmap_gate_endisable(hw, 1);
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}
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static void clk_regmap_gate_disable(struct clk_hw *hw)
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{
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clk_regmap_gate_endisable(hw, 0);
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}
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static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
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unsigned int val;
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regmap_read(clk->map, gate->offset, &val);
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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val ^= BIT(gate->bit_idx);
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val &= BIT(gate->bit_idx);
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return val ? 1 : 0;
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}
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const struct clk_ops clk_regmap_gate_ops = {
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.enable = clk_regmap_gate_enable,
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.disable = clk_regmap_gate_disable,
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.is_enabled = clk_regmap_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
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const struct clk_ops clk_regmap_gate_ro_ops = {
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.is_enabled = clk_regmap_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);
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static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
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unsigned int val;
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int ret;
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ret = regmap_read(clk->map, div->offset, &val);
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if (ret)
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/* Gives a hint that something is wrong */
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return 0;
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val >>= div->shift;
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val &= clk_div_mask(div->width);
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return divider_recalc_rate(hw, prate, val, div->table, div->flags,
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div->width);
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}
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static int clk_regmap_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
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unsigned int val;
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int ret;
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/* if read only, just return current value */
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if (div->flags & CLK_DIVIDER_READ_ONLY) {
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ret = regmap_read(clk->map, div->offset, &val);
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if (ret)
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return ret;
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val >>= div->shift;
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val &= clk_div_mask(div->width);
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return divider_ro_determine_rate(hw, req, div->table,
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div->width, div->flags, val);
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}
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return divider_determine_rate(hw, req, div->table, div->width,
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div->flags);
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}
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static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
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unsigned int val;
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int ret;
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ret = divider_get_val(rate, parent_rate, div->table, div->width,
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div->flags);
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if (ret < 0)
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return ret;
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val = (unsigned int)ret << div->shift;
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return regmap_update_bits(clk->map, div->offset,
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clk_div_mask(div->width) << div->shift, val);
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};
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/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
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const struct clk_ops clk_regmap_divider_ops = {
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.recalc_rate = clk_regmap_div_recalc_rate,
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.determine_rate = clk_regmap_div_determine_rate,
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.set_rate = clk_regmap_div_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
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const struct clk_ops clk_regmap_divider_ro_ops = {
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.recalc_rate = clk_regmap_div_recalc_rate,
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.determine_rate = clk_regmap_div_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
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static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
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unsigned int val;
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int ret;
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ret = regmap_read(clk->map, mux->offset, &val);
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if (ret)
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return ret;
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val >>= mux->shift;
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val &= mux->mask;
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return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
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}
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static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
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unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index);
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return regmap_update_bits(clk->map, mux->offset,
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mux->mask << mux->shift,
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val << mux->shift);
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}
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static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
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return clk_mux_determine_rate_flags(hw, req, mux->flags);
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}
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const struct clk_ops clk_regmap_mux_ops = {
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.get_parent = clk_regmap_mux_get_parent,
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.set_parent = clk_regmap_mux_set_parent,
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.determine_rate = clk_regmap_mux_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
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const struct clk_ops clk_regmap_mux_ro_ops = {
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.get_parent = clk_regmap_mux_get_parent,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops);
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MODULE_DESCRIPTION("Amlogic regmap backed clock driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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