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![Wei Yongjun](/assets/img/avatar_default.png)
The sparse tool complains as follows:
drivers/clk/qcom/clk-cpu-8996.c:341:19: warning:
symbol 'cpu_msm8996_clks' was not declared. Should it be static?
This variable is not used outside of clk-cpu-8996.c, so this commit
marks it static.
Fixes: 03e342dc45
("clk: qcom: Add CPU clock driver for msm8996")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20200714142155.35085-1-weiyongjun1@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
538 lines
14 KiB
C
538 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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/*
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* Each of the CPU clusters (Power and Perf) on msm8996 are
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* clocked via 2 PLLs, a primary and alternate. There are also
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* 2 Mux'es, a primary and secondary all connected together
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* as shown below
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*
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* +-------+
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* XO | |
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* +------------------>0 |
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* | |
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* PLL/2 | SMUX +----+
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* +------->1 | |
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* | | | |
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* | +-------+ | +-------+
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* | +---->0 |
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* | | |
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* +---------------+ | +----------->1 | CPU clk
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* |Primary PLL +----+ PLL_EARLY | | +------>
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* | +------+-----------+ +------>2 PMUX |
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* +---------------+ | | | |
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* | +------+ | +-->3 |
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* +--^+ ACD +-----+ | +-------+
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* +---------------+ +------+ |
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* |Alt PLL | |
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* | +---------------------------+
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* +---------------+ PLL_EARLY
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*
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* The primary PLL is what drives the CPU clk, except for times
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* when we are reprogramming the PLL itself (for rate changes) when
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* we temporarily switch to an alternate PLL.
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*
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* The primary PLL operates on a single VCO range, between 600MHz
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* and 3GHz. However the CPUs do support OPPs with frequencies
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* between 300MHz and 600MHz. In order to support running the CPUs
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* at those frequencies we end up having to lock the PLL at twice
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* the rate and drive the CPU clk via the PLL/2 output and SMUX.
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*
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* So for frequencies above 600MHz we follow the following path
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* Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
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* and for frequencies between 300MHz and 600MHz we follow
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* Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
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*
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* ACD stands for Adaptive Clock Distribution and is used to
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* detect voltage droops.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <soc/qcom/kryo-l2-accessors.h>
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#include "clk-alpha-pll.h"
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#include "clk-regmap.h"
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enum _pmux_input {
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DIV_2_INDEX = 0,
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PLL_INDEX,
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ACD_INDEX,
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ALT_INDEX,
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NUM_OF_PMUX_INPUTS
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};
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#define DIV_2_THRESHOLD 600000000
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#define PWRCL_REG_OFFSET 0x0
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#define PERFCL_REG_OFFSET 0x80000
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#define MUX_OFFSET 0x40
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#define ALT_PLL_OFFSET 0x100
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#define SSSCTL_OFFSET 0x160
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static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1c,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_TEST_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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};
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static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_USER_CTL_U] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_TEST_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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};
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/* PLLs */
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static const struct alpha_pll_config hfpll_config = {
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.l = 60,
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.config_ctl_val = 0x200d4aa8,
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.config_ctl_hi_val = 0x006,
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.pre_div_mask = BIT(12),
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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static struct clk_alpha_pll perfcl_pll = {
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.offset = PERFCL_REG_OFFSET,
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
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static struct clk_alpha_pll pwrcl_pll = {
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.offset = PWRCL_REG_OFFSET,
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
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static const struct pll_vco alt_pll_vco_modes[] = {
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VCO(3, 250000000, 500000000),
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VCO(2, 500000000, 750000000),
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VCO(1, 750000000, 1000000000),
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VCO(0, 1000000000, 2150400000),
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};
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static const struct alpha_pll_config altpll_config = {
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.l = 16,
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.vco_val = 0x3 << 20,
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.vco_mask = 0x3 << 20,
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.config_ctl_val = 0x4001051b,
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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static struct clk_alpha_pll perfcl_alt_pll = {
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.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_alt_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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static struct clk_alpha_pll pwrcl_alt_pll = {
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.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_alt_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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struct clk_cpu_8996_mux {
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u32 reg;
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u8 shift;
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u8 width;
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struct notifier_block nb;
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struct clk_hw *pll;
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struct clk_hw *pll_div_2;
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struct clk_regmap clkr;
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};
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static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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#define to_clk_cpu_8996_mux_nb(_nb) \
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container_of(_nb, struct clk_cpu_8996_mux, nb)
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static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
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{
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return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
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}
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static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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u32 mask = GENMASK(cpuclk->width - 1, 0);
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u32 val;
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regmap_read(clkr->regmap, cpuclk->reg, &val);
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val >>= cpuclk->shift;
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return val & mask;
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}
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static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift);
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u32 val;
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val = index;
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val <<= cpuclk->shift;
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return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
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}
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static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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struct clk_hw *parent = cpuclk->pll;
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if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
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if (req->rate < (DIV_2_THRESHOLD / 2))
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return -EINVAL;
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parent = cpuclk->pll_div_2;
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}
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req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
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req->best_parent_hw = parent;
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return 0;
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}
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static const struct clk_ops clk_cpu_8996_mux_ops = {
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.set_parent = clk_cpu_8996_mux_set_parent,
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.get_parent = clk_cpu_8996_mux_get_parent,
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.determine_rate = clk_cpu_8996_mux_determine_rate,
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};
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static struct clk_cpu_8996_mux pwrcl_smux = {
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.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
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.shift = 2,
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.width = 2,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_smux",
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.parent_names = (const char *[]){
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"xo",
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"pwrcl_pll_main",
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},
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.num_parents = 2,
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.ops = &clk_cpu_8996_mux_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_cpu_8996_mux perfcl_smux = {
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.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
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.shift = 2,
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.width = 2,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_smux",
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.parent_names = (const char *[]){
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"xo",
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"perfcl_pll_main",
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},
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.num_parents = 2,
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.ops = &clk_cpu_8996_mux_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_cpu_8996_mux pwrcl_pmux = {
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.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
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.shift = 0,
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.width = 2,
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.pll = &pwrcl_pll.clkr.hw,
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.pll_div_2 = &pwrcl_smux.clkr.hw,
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.nb.notifier_call = cpu_clk_notifier_cb,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_pmux",
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.parent_names = (const char *[]){
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"pwrcl_smux",
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"pwrcl_pll",
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"pwrcl_pll_acd",
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"pwrcl_alt_pll",
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},
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.num_parents = 4,
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.ops = &clk_cpu_8996_mux_ops,
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/* CPU clock is critical and should never be gated */
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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},
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};
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static struct clk_cpu_8996_mux perfcl_pmux = {
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.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
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.shift = 0,
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.width = 2,
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.pll = &perfcl_pll.clkr.hw,
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.pll_div_2 = &perfcl_smux.clkr.hw,
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.nb.notifier_call = cpu_clk_notifier_cb,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_pmux",
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.parent_names = (const char *[]){
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"perfcl_smux",
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"perfcl_pll",
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"perfcl_pll_acd",
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"perfcl_alt_pll",
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},
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.num_parents = 4,
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.ops = &clk_cpu_8996_mux_ops,
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/* CPU clock is critical and should never be gated */
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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},
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};
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static const struct regmap_config cpu_msm8996_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x80210,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static struct clk_regmap *cpu_msm8996_clks[] = {
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&perfcl_pll.clkr,
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&pwrcl_pll.clkr,
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&perfcl_alt_pll.clkr,
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&pwrcl_alt_pll.clkr,
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&perfcl_smux.clkr,
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&pwrcl_smux.clkr,
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&perfcl_pmux.clkr,
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&pwrcl_pmux.clkr,
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};
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static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
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struct regmap *regmap)
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{
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int i, ret;
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perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
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"perfcl_pll",
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CLK_SET_RATE_PARENT,
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1, 2);
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if (IS_ERR(perfcl_smux.pll)) {
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dev_err(dev, "Failed to initialize perfcl_pll_main\n");
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return PTR_ERR(perfcl_smux.pll);
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}
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pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
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"pwrcl_pll",
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CLK_SET_RATE_PARENT,
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1, 2);
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if (IS_ERR(pwrcl_smux.pll)) {
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dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
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clk_hw_unregister(perfcl_smux.pll);
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return PTR_ERR(pwrcl_smux.pll);
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}
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for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
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ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
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if (ret) {
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clk_hw_unregister(perfcl_smux.pll);
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clk_hw_unregister(pwrcl_smux.pll);
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return ret;
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}
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}
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clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
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clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
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clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
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clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
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/* Enable alt PLLs */
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clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
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clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
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clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
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clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
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return ret;
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}
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static int qcom_cpu_clk_msm8996_unregister_clks(void)
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{
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int ret = 0;
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ret = clk_notifier_unregister(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
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if (ret)
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return ret;
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ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
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if (ret)
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return ret;
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clk_hw_unregister(perfcl_smux.pll);
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clk_hw_unregister(pwrcl_smux.pll);
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return 0;
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}
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#define CPU_AFINITY_MASK 0xFFF
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#define PWRCL_CPU_REG_MASK 0x3
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#define PERFCL_CPU_REG_MASK 0x103
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#define L2ACDCR_REG 0x580ULL
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#define L2ACDTD_REG 0x581ULL
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#define L2ACDDVMRC_REG 0x584ULL
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#define L2ACDSSCR_REG 0x589ULL
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static DEFINE_SPINLOCK(qcom_clk_acd_lock);
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static void __iomem *base;
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static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base)
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{
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u64 hwid;
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unsigned long flags;
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spin_lock_irqsave(&qcom_clk_acd_lock, flags);
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hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
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kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
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kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
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kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
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if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
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writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET);
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kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
|
|
}
|
|
|
|
if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) {
|
|
kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
|
|
writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);
|
|
}
|
|
|
|
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
|
|
void *data)
|
|
{
|
|
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
|
|
struct clk_notifier_data *cnd = data;
|
|
int ret;
|
|
|
|
switch (event) {
|
|
case PRE_RATE_CHANGE:
|
|
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
|
|
qcom_cpu_clk_msm8996_acd_init(base);
|
|
break;
|
|
case POST_RATE_CHANGE:
|
|
if (cnd->new_rate < DIV_2_THRESHOLD)
|
|
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
|
|
DIV_2_INDEX);
|
|
else
|
|
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
|
|
ACD_INDEX);
|
|
break;
|
|
default:
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
return notifier_from_errno(ret);
|
|
};
|
|
|
|
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
struct clk_hw_onecell_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
|
|
if (ret)
|
|
return ret;
|
|
|
|
qcom_cpu_clk_msm8996_acd_init(base);
|
|
|
|
data->hws[0] = &pwrcl_pmux.clkr.hw;
|
|
data->hws[1] = &perfcl_pmux.clkr.hw;
|
|
data->num = 2;
|
|
|
|
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
|
|
}
|
|
|
|
static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev)
|
|
{
|
|
return qcom_cpu_clk_msm8996_unregister_clks();
|
|
}
|
|
|
|
static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
|
|
{ .compatible = "qcom,msm8996-apcc" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
|
|
|
|
static struct platform_driver qcom_cpu_clk_msm8996_driver = {
|
|
.probe = qcom_cpu_clk_msm8996_driver_probe,
|
|
.remove = qcom_cpu_clk_msm8996_driver_remove,
|
|
.driver = {
|
|
.name = "qcom-msm8996-apcc",
|
|
.of_match_table = qcom_cpu_clk_msm8996_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(qcom_cpu_clk_msm8996_driver);
|
|
|
|
MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
|
|
MODULE_LICENSE("GPL v2");
|