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470e3f0d0b
According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
76 lines
2 KiB
C
76 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen4 Clock Pulse Generator
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
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enum rcar_gen4_clk_types {
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CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN4_PLL1,
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CLK_TYPE_GEN4_PLL2,
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CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
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CLK_TYPE_GEN4_PLL3,
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_PLL6,
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CLK_TYPE_GEN4_SDSRC,
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CLK_TYPE_GEN4_SDH,
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CLK_TYPE_GEN4_SD,
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CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN4_Z,
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CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_RPCSRC,
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CLK_TYPE_GEN4_RPC,
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CLK_TYPE_GEN4_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN4_SOC_BASE,
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};
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#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
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#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
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#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen4_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll2_mult;
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u8 pll2_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 pll6_mult;
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u8 pll6_div;
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u8 osc_prediv;
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};
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#define CPG_RPCCKCR 0x874
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#define SD0CKCR1 0x8a4
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struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers);
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int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
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unsigned int clk_extalr, u32 mode);
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#endif
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