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7ec03b588d
The PRCM CCU drivers depend on clocks provided by other CCU drivers. For example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by the SoC's main CCU. However, sun8i-r-ccu is an early OF clock provider, and many of the main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that the consumer clocks will be orphaned until the supplier driver is bound. This can be avoided by converting the remaining CCUs to use platform drivers. Then fw_devlink will ensure the drivers are bound in the optimal order. The sun5i CCU is the only one which actually needs to be an early clock provider, because it provides the clock for the system timer. That one is left alone. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-4-samuel@sholland.org
301 lines
7.8 KiB
C
301 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_nm.h"
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#include "ccu-sun8i-r.h"
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static const struct clk_parent_data ar100_parents[] = {
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{ .fw_name = "losc" },
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{ .fw_name = "hosc" },
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{ .fw_name = "pll-periph" },
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{ .fw_name = "iosc" },
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};
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static const struct ccu_mux_var_prediv ar100_predivs[] = {
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{ .index = 2, .shift = 8, .width = 5 },
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};
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static struct ccu_div ar100_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 16,
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.width = 2,
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.var_predivs = ar100_predivs,
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.n_var_predivs = ARRAY_SIZE(ar100_predivs),
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},
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.common = {
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.reg = 0x00,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS_DATA("ar100",
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ar100_parents,
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&ccu_div_ops,
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0),
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},
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};
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static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
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static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
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/*
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* Define the parent as an array that can be reused to save space
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* instead of having compound literals for each gate. Also have it
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* non-const so we can change it on the A83T.
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*/
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static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
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static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
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apb0_gate_parent, 0x28, BIT(0), 0);
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static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
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apb0_gate_parent, 0x28, BIT(1), 0);
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static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
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apb0_gate_parent, 0x28, BIT(2), 0);
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static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
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apb0_gate_parent, 0x28, BIT(3), 0);
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static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
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apb0_gate_parent, 0x28, BIT(4), 0);
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static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c",
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apb0_gate_parent, 0x28, BIT(6), 0);
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static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd",
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apb0_gate_parent, 0x28, BIT(7), 0);
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static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
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r_mod0_default_parents, 0x54,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static const struct clk_parent_data a83t_r_mod0_parents[] = {
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{ .fw_name = "iosc" },
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{ .fw_name = "hosc" },
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};
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static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
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{ .index = 0, .div = 16 },
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};
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static struct ccu_mp a83t_ir_clk = {
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.enable = BIT(31),
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.m = _SUNXI_CCU_DIV(0, 4),
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.p = _SUNXI_CCU_DIV(16, 2),
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.mux = {
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.shift = 24,
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.width = 2,
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.fixed_predivs = a83t_ir_predivs,
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.n_predivs = ARRAY_SIZE(a83t_ir_predivs),
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},
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.common = {
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.reg = 0x54,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS_DATA("ir",
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a83t_r_mod0_parents,
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&ccu_mp_ops,
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0),
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},
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};
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static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
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&ar100_clk.common,
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&apb0_clk.common,
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&apb0_pio_clk.common,
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&apb0_ir_clk.common,
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&apb0_timer_clk.common,
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&apb0_rsb_clk.common,
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&apb0_uart_clk.common,
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&apb0_i2c_clk.common,
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&apb0_twd_clk.common,
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&a83t_ir_clk.common,
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};
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static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
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&ar100_clk.common,
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&apb0_clk.common,
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&apb0_pio_clk.common,
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&apb0_ir_clk.common,
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&apb0_timer_clk.common,
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&apb0_uart_clk.common,
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&apb0_i2c_clk.common,
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&apb0_twd_clk.common,
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&ir_clk.common,
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};
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static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
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&ar100_clk.common,
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&apb0_clk.common,
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&apb0_pio_clk.common,
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&apb0_ir_clk.common,
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&apb0_timer_clk.common,
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&apb0_rsb_clk.common,
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&apb0_uart_clk.common,
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&apb0_i2c_clk.common,
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&apb0_twd_clk.common,
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&ir_clk.common,
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};
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static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
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.hws = {
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[CLK_AR100] = &ar100_clk.common.hw,
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[CLK_AHB0] = &ahb0_clk.hw,
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[CLK_APB0] = &apb0_clk.common.hw,
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[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
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[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
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[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
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[CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
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[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
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[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
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[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
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[CLK_IR] = &a83t_ir_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
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.hws = {
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[CLK_AR100] = &ar100_clk.common.hw,
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[CLK_AHB0] = &ahb0_clk.hw,
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[CLK_APB0] = &apb0_clk.common.hw,
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[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
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[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
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[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
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[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
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[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
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[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
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[CLK_IR] = &ir_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
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.hws = {
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[CLK_AR100] = &ar100_clk.common.hw,
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[CLK_AHB0] = &ahb0_clk.hw,
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[CLK_APB0] = &apb0_clk.common.hw,
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[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
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[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
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[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
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[CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
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[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
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[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
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[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
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[CLK_IR] = &ir_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
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[RST_APB0_IR] = { 0xb0, BIT(1) },
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[RST_APB0_TIMER] = { 0xb0, BIT(2) },
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[RST_APB0_RSB] = { 0xb0, BIT(3) },
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[RST_APB0_UART] = { 0xb0, BIT(4) },
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[RST_APB0_I2C] = { 0xb0, BIT(6) },
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};
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static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
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[RST_APB0_IR] = { 0xb0, BIT(1) },
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[RST_APB0_TIMER] = { 0xb0, BIT(2) },
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[RST_APB0_UART] = { 0xb0, BIT(4) },
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[RST_APB0_I2C] = { 0xb0, BIT(6) },
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};
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static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
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[RST_APB0_IR] = { 0xb0, BIT(1) },
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[RST_APB0_TIMER] = { 0xb0, BIT(2) },
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[RST_APB0_RSB] = { 0xb0, BIT(3) },
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[RST_APB0_UART] = { 0xb0, BIT(4) },
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[RST_APB0_I2C] = { 0xb0, BIT(6) },
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};
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static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
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.ccu_clks = sun8i_a83t_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
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.hw_clks = &sun8i_a83t_r_hw_clks,
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.resets = sun8i_a83t_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets),
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};
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static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
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.ccu_clks = sun8i_h3_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
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.hw_clks = &sun8i_h3_r_hw_clks,
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.resets = sun8i_h3_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
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.ccu_clks = sun50i_a64_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
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.hw_clks = &sun50i_a64_r_hw_clks,
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.resets = sun50i_a64_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
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};
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static int sun8i_r_ccu_probe(struct platform_device *pdev)
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{
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const struct sunxi_ccu_desc *desc;
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void __iomem *reg;
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desc = of_device_get_match_data(&pdev->dev);
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if (!desc)
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return -EINVAL;
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
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}
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static const struct of_device_id sun8i_r_ccu_ids[] = {
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{
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.compatible = "allwinner,sun8i-a83t-r-ccu",
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.data = &sun8i_a83t_r_ccu_desc,
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},
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{
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.compatible = "allwinner,sun8i-h3-r-ccu",
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.data = &sun8i_h3_r_ccu_desc,
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},
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{
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.compatible = "allwinner,sun50i-a64-r-ccu",
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.data = &sun50i_a64_r_ccu_desc,
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},
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{ }
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};
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static struct platform_driver sun8i_r_ccu_driver = {
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.probe = sun8i_r_ccu_probe,
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.driver = {
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.name = "sun8i-r-ccu",
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.suppress_bind_attrs = true,
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.of_match_table = sun8i_r_ccu_ids,
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},
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};
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module_platform_driver(sun8i_r_ccu_driver);
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MODULE_IMPORT_NS(SUNXI_CCU);
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MODULE_LICENSE("GPL");
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