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![Shubhrajyoti Datta](/assets/img/avatar_default.png)
Currently the return value of of_clk_add_hw_provider is ignored. lets check and return value. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/20210818065929.12835-2-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
792 lines
20 KiB
C
792 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC clock controller
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*
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* Copyright (C) 2016-2019 Xilinx
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*
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* Based on drivers/clk/zynq/clkc.c
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "clk-zynqmp.h"
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#define MAX_PARENT 100
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#define MAX_NODES 6
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#define MAX_NAME_LEN 50
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/* Flags for parents */
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#define PARENT_CLK_SELF 0
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#define PARENT_CLK_NODE1 1
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#define PARENT_CLK_NODE2 2
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#define PARENT_CLK_NODE3 3
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#define PARENT_CLK_NODE4 4
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#define PARENT_CLK_EXTERNAL 5
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#define END_OF_CLK_NAME "END_OF_CLK"
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#define END_OF_TOPOLOGY_NODE 1
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#define END_OF_PARENTS 1
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#define RESERVED_CLK_NAME ""
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#define CLK_GET_NAME_RESP_LEN 16
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#define CLK_GET_TOPOLOGY_RESP_WORDS 3
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#define CLK_GET_PARENTS_RESP_WORDS 3
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#define CLK_GET_ATTR_RESP_WORDS 1
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enum clk_type {
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CLK_TYPE_OUTPUT,
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CLK_TYPE_EXTERNAL,
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};
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/**
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* struct clock_parent - Clock parent
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* @name: Parent name
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* @id: Parent clock ID
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* @flag: Parent flags
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*/
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struct clock_parent {
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char name[MAX_NAME_LEN];
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int id;
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u32 flag;
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};
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/**
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* struct zynqmp_clock - Clock
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* @clk_name: Clock name
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* @valid: Validity flag of clock
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* @type: Clock type (Output/External)
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* @node: Clock topology nodes
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* @num_nodes: Number of nodes present in topology
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* @parent: Parent of clock
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* @num_parents: Number of parents of clock
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* @clk_id: Clock id
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*/
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struct zynqmp_clock {
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char clk_name[MAX_NAME_LEN];
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u32 valid;
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enum clk_type type;
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struct clock_topology node[MAX_NODES];
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u32 num_nodes;
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struct clock_parent parent[MAX_PARENT];
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u32 num_parents;
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u32 clk_id;
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};
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struct name_resp {
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char name[CLK_GET_NAME_RESP_LEN];
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};
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struct topology_resp {
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#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
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#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)
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#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
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#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
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u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
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};
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struct parents_resp {
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#define NA_PARENT 0xFFFFFFFF
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#define DUMMY_PARENT 0xFFFFFFFE
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#define CLK_PARENTS_ID GENMASK(15, 0)
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#define CLK_PARENTS_FLAGS GENMASK(31, 16)
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u32 parents[CLK_GET_PARENTS_RESP_WORDS];
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};
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struct attr_resp {
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#define CLK_ATTR_VALID BIT(0)
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#define CLK_ATTR_TYPE BIT(2)
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#define CLK_ATTR_NODE_INDEX GENMASK(13, 0)
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#define CLK_ATTR_NODE_TYPE GENMASK(19, 14)
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#define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20)
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#define CLK_ATTR_NODE_CLASS GENMASK(31, 26)
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u32 attr[CLK_GET_ATTR_RESP_WORDS];
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};
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static const char clk_type_postfix[][10] = {
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[TYPE_INVALID] = "",
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[TYPE_MUX] = "_mux",
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[TYPE_GATE] = "",
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[TYPE_DIV1] = "_div1",
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[TYPE_DIV2] = "_div2",
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[TYPE_FIXEDFACTOR] = "_ff",
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[TYPE_PLL] = ""
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};
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static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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= {
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[TYPE_INVALID] = NULL,
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[TYPE_MUX] = zynqmp_clk_register_mux,
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[TYPE_PLL] = zynqmp_clk_register_pll,
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[TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
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[TYPE_DIV1] = zynqmp_clk_register_divider,
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[TYPE_DIV2] = zynqmp_clk_register_divider,
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[TYPE_GATE] = zynqmp_clk_register_gate
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};
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static struct zynqmp_clock *clock;
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static struct clk_hw_onecell_data *zynqmp_data;
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static unsigned int clock_max_idx;
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/**
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* zynqmp_is_valid_clock() - Check whether clock is valid or not
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* @clk_id: Clock index
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*
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* Return: 1 if clock is valid, 0 if clock is invalid else error code
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*/
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static inline int zynqmp_is_valid_clock(u32 clk_id)
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{
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if (clk_id >= clock_max_idx)
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return -ENODEV;
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return clock[clk_id].valid;
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}
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/**
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* zynqmp_get_clock_name() - Get name of clock from Clock index
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* @clk_id: Clock index
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* @clk_name: Name of clock
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
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{
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int ret;
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ret = zynqmp_is_valid_clock(clk_id);
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if (ret == 1) {
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strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
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return 0;
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}
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return ret == 0 ? -EINVAL : ret;
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}
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/**
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* zynqmp_get_clock_type() - Get type of clock
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* @clk_id: Clock index
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* @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
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{
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int ret;
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ret = zynqmp_is_valid_clock(clk_id);
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if (ret == 1) {
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*type = clock[clk_id].type;
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return 0;
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}
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return ret == 0 ? -EINVAL : ret;
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}
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/**
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* zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
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* @nclocks: Number of clocks in system/board.
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*
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* Call firmware API to get number of clocks.
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*
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* Return: 0 on success else error code.
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*/
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static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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*nclocks = ret_payload[1];
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return ret;
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}
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/**
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* zynqmp_pm_clock_get_name() - Get the name of clock for given id
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* @clock_id: ID of the clock to be queried
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* @response: Name of the clock with the given id
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*
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* This function is used to get name of clock specified by given
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* clock ID.
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*
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* Return: Returns 0
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*/
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static int zynqmp_pm_clock_get_name(u32 clock_id,
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struct name_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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qdata.qid = PM_QID_CLOCK_GET_NAME;
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qdata.arg1 = clock_id;
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zynqmp_pm_query_data(qdata, ret_payload);
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memcpy(response, ret_payload, sizeof(*response));
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return 0;
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}
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/**
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* zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
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* @clock_id: ID of the clock to be queried
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* @index: Node index of clock topology
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* @response: Buffer used for the topology response
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*
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* This function is used to get topology information for the clock
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* specified by given clock ID.
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*
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* This API will return 3 node of topology with a single response. To get
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* other nodes, master should call same API in loop with new
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* index till error is returned. E.g First call should have
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* index 0 which will return nodes 0,1 and 2. Next call, index
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* should be 3 which will return nodes 3,4 and 5 and so on.
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
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struct topology_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
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qdata.arg1 = clock_id;
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qdata.arg2 = index;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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memcpy(response, &ret_payload[1], sizeof(*response));
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return ret;
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}
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unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
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{
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unsigned long ccf_flag = 0;
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if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
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ccf_flag |= CLK_SET_RATE_GATE;
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if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
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ccf_flag |= CLK_SET_PARENT_GATE;
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if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
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ccf_flag |= CLK_SET_RATE_PARENT;
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if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
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ccf_flag |= CLK_IGNORE_UNUSED;
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if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
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ccf_flag |= CLK_SET_RATE_NO_REPARENT;
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if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
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ccf_flag |= CLK_IS_CRITICAL;
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return ccf_flag;
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}
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/**
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* zynqmp_clk_register_fixed_factor() - Register fixed factor with the
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* clock framework
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* @name: Name of this clock
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* @clk_id: Clock ID
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware to the registered clock
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*/
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struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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u32 mult, div;
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struct clk_hw *hw;
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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unsigned long flag;
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qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
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qdata.arg1 = clk_id;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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if (ret)
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return ERR_PTR(ret);
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mult = ret_payload[1];
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div = ret_payload[2];
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flag = zynqmp_clk_map_common_ccf_flags(nodes->flag);
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hw = clk_hw_register_fixed_factor(NULL, name,
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parents[0],
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flag, mult,
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div);
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return hw;
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}
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/**
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* zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
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* @clock_id: Clock ID
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* @index: Parent index
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* @response: Parents of the given clock
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*
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* This function is used to get 3 parents for the clock specified by
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* given clock ID.
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*
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* This API will return 3 parents with a single response. To get
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* other parents, master should call same API in loop with new
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* parent index till error is returned. E.g First call should have
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* index 0 which will return parents 0,1 and 2. Next call, index
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* should be 3 which will return parent 3,4 and 5 and so on.
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index,
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struct parents_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_PARENTS;
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qdata.arg1 = clock_id;
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qdata.arg2 = index;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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memcpy(response, &ret_payload[1], sizeof(*response));
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return ret;
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}
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/**
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* zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
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* @clock_id: Clock ID
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* @response: Clock attributes response
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*
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* This function is used to get clock's attributes(e.g. valid, clock type, etc).
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_pm_clock_get_attributes(u32 clock_id,
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struct attr_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
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qdata.arg1 = clock_id;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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memcpy(response, &ret_payload[1], sizeof(*response));
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return ret;
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}
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/**
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* __zynqmp_clock_get_topology() - Get topology data of clock from firmware
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* response data
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* @topology: Clock topology
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* @response: Clock topology data received from firmware
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* @nnodes: Number of nodes
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*
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* Return: 0 on success else error+reason
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*/
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static int __zynqmp_clock_get_topology(struct clock_topology *topology,
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struct topology_resp *response,
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u32 *nnodes)
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{
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int i;
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u32 type;
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for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
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type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
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if (type == TYPE_INVALID)
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return END_OF_TOPOLOGY_NODE;
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topology[*nnodes].type = type;
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topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
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response->topology[i]);
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topology[*nnodes].type_flag =
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FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
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response->topology[i]);
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topology[*nnodes].custom_type_flag =
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FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS,
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response->topology[i]);
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(*nnodes)++;
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}
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return 0;
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}
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/**
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* zynqmp_clock_get_topology() - Get topology of clock from firmware using
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* PM_API
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* @clk_id: Clock index
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* @topology: Clock topology
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* @num_nodes: Number of nodes
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_clock_get_topology(u32 clk_id,
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struct clock_topology *topology,
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u32 *num_nodes)
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{
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int j, ret;
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struct topology_resp response = { };
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*num_nodes = 0;
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for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) {
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ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
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&response);
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if (ret)
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return ret;
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ret = __zynqmp_clock_get_topology(topology, &response,
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num_nodes);
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if (ret == END_OF_TOPOLOGY_NODE)
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return 0;
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}
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return 0;
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}
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/**
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* __zynqmp_clock_get_parents() - Get parents info of clock from firmware
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* response data
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* @parents: Clock parents
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* @response: Clock parents data received from firmware
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* @nparent: Number of parent
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*
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* Return: 0 on success else error+reason
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*/
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static int __zynqmp_clock_get_parents(struct clock_parent *parents,
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struct parents_resp *response,
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u32 *nparent)
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{
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int i;
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struct clock_parent *parent;
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for (i = 0; i < ARRAY_SIZE(response->parents); i++) {
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if (response->parents[i] == NA_PARENT)
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return END_OF_PARENTS;
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parent = &parents[i];
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parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);
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if (response->parents[i] == DUMMY_PARENT) {
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strcpy(parent->name, "dummy_name");
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parent->flag = 0;
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} else {
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parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,
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response->parents[i]);
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if (zynqmp_get_clock_name(parent->id, parent->name))
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continue;
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}
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*nparent += 1;
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}
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return 0;
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}
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/**
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* zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
|
|
* @clk_id: Clock index
|
|
* @parents: Clock parents
|
|
* @num_parents: Total number of parents
|
|
*
|
|
* Return: 0 on success else error+reason
|
|
*/
|
|
static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
|
|
u32 *num_parents)
|
|
{
|
|
int j = 0, ret;
|
|
struct parents_resp response = { };
|
|
|
|
*num_parents = 0;
|
|
do {
|
|
/* Get parents from firmware */
|
|
ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
|
|
&response);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = __zynqmp_clock_get_parents(&parents[j], &response,
|
|
num_parents);
|
|
if (ret == END_OF_PARENTS)
|
|
return 0;
|
|
j += ARRAY_SIZE(response.parents);
|
|
} while (*num_parents <= MAX_PARENT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_get_parent_list() - Create list of parents name
|
|
* @np: Device node
|
|
* @clk_id: Clock index
|
|
* @parent_list: List of parent's name
|
|
* @num_parents: Total number of parents
|
|
*
|
|
* Return: 0 on success else error+reason
|
|
*/
|
|
static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
|
|
const char **parent_list, u32 *num_parents)
|
|
{
|
|
int i = 0, ret;
|
|
u32 total_parents = clock[clk_id].num_parents;
|
|
struct clock_topology *clk_nodes;
|
|
struct clock_parent *parents;
|
|
|
|
clk_nodes = clock[clk_id].node;
|
|
parents = clock[clk_id].parent;
|
|
|
|
for (i = 0; i < total_parents; i++) {
|
|
if (!parents[i].flag) {
|
|
parent_list[i] = parents[i].name;
|
|
} else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
|
|
ret = of_property_match_string(np, "clock-names",
|
|
parents[i].name);
|
|
if (ret < 0)
|
|
strcpy(parents[i].name, "dummy_name");
|
|
parent_list[i] = parents[i].name;
|
|
} else {
|
|
strcat(parents[i].name,
|
|
clk_type_postfix[clk_nodes[parents[i].flag - 1].
|
|
type]);
|
|
parent_list[i] = parents[i].name;
|
|
}
|
|
}
|
|
|
|
*num_parents = total_parents;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_register_clk_topology() - Register clock topology
|
|
* @clk_id: Clock index
|
|
* @clk_name: Clock Name
|
|
* @num_parents: Total number of parents
|
|
* @parent_names: List of parents name
|
|
*
|
|
* Return: Returns either clock hardware or error+reason
|
|
*/
|
|
static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
|
|
int num_parents,
|
|
const char **parent_names)
|
|
{
|
|
int j;
|
|
u32 num_nodes, clk_dev_id;
|
|
char *clk_out[MAX_NODES];
|
|
struct clock_topology *nodes;
|
|
struct clk_hw *hw = NULL;
|
|
|
|
nodes = clock[clk_id].node;
|
|
num_nodes = clock[clk_id].num_nodes;
|
|
clk_dev_id = clock[clk_id].clk_id;
|
|
|
|
for (j = 0; j < num_nodes; j++) {
|
|
/*
|
|
* Clock name received from firmware is output clock name.
|
|
* Intermediate clock names are postfixed with type of clock.
|
|
*/
|
|
if (j != (num_nodes - 1)) {
|
|
clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name,
|
|
clk_type_postfix[nodes[j].type]);
|
|
} else {
|
|
clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name);
|
|
}
|
|
|
|
if (!clk_topology[nodes[j].type])
|
|
continue;
|
|
|
|
hw = (*clk_topology[nodes[j].type])(clk_out[j], clk_dev_id,
|
|
parent_names,
|
|
num_parents,
|
|
&nodes[j]);
|
|
if (IS_ERR(hw))
|
|
pr_warn_once("%s() 0x%x: %s register fail with %ld\n",
|
|
__func__, clk_dev_id, clk_name,
|
|
PTR_ERR(hw));
|
|
|
|
parent_names[0] = clk_out[j];
|
|
}
|
|
|
|
for (j = 0; j < num_nodes; j++)
|
|
kfree(clk_out[j]);
|
|
|
|
return hw;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_register_clocks() - Register clocks
|
|
* @np: Device node
|
|
*
|
|
* Return: 0 on success else error code
|
|
*/
|
|
static int zynqmp_register_clocks(struct device_node *np)
|
|
{
|
|
int ret;
|
|
u32 i, total_parents = 0, type = 0;
|
|
const char *parent_names[MAX_PARENT];
|
|
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
char clk_name[MAX_NAME_LEN];
|
|
|
|
/* get clock name, continue to next clock if name not found */
|
|
if (zynqmp_get_clock_name(i, clk_name))
|
|
continue;
|
|
|
|
/* Check if clock is valid and output clock.
|
|
* Do not register invalid or external clock.
|
|
*/
|
|
ret = zynqmp_get_clock_type(i, &type);
|
|
if (ret || type != CLK_TYPE_OUTPUT)
|
|
continue;
|
|
|
|
/* Get parents of clock*/
|
|
if (zynqmp_get_parent_list(np, i, parent_names,
|
|
&total_parents)) {
|
|
WARN_ONCE(1, "No parents found for %s\n",
|
|
clock[i].clk_name);
|
|
continue;
|
|
}
|
|
|
|
zynqmp_data->hws[i] =
|
|
zynqmp_register_clk_topology(i, clk_name,
|
|
total_parents,
|
|
parent_names);
|
|
}
|
|
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
if (IS_ERR(zynqmp_data->hws[i])) {
|
|
pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
|
|
clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
|
|
WARN_ON(1);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_get_clock_info() - Get clock information from firmware using PM_API
|
|
*/
|
|
static void zynqmp_get_clock_info(void)
|
|
{
|
|
int i, ret;
|
|
u32 type = 0;
|
|
u32 nodetype, subclass, class;
|
|
struct attr_resp attr;
|
|
struct name_resp name;
|
|
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
ret = zynqmp_pm_clock_get_attributes(i, &attr);
|
|
if (ret)
|
|
continue;
|
|
|
|
clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
|
|
/* skip query for Invalid clock */
|
|
ret = zynqmp_is_valid_clock(i);
|
|
if (ret != CLK_ATTR_VALID)
|
|
continue;
|
|
|
|
clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
|
|
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
|
|
|
|
nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]);
|
|
subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]);
|
|
class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]);
|
|
|
|
clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
|
|
FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) |
|
|
FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) |
|
|
FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
|
|
|
|
zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
|
|
if (!strcmp(name.name, RESERVED_CLK_NAME))
|
|
continue;
|
|
strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
|
|
}
|
|
|
|
/* Get topology of all clock */
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
ret = zynqmp_get_clock_type(i, &type);
|
|
if (ret || type != CLK_TYPE_OUTPUT)
|
|
continue;
|
|
|
|
ret = zynqmp_clock_get_topology(i, clock[i].node,
|
|
&clock[i].num_nodes);
|
|
if (ret)
|
|
continue;
|
|
|
|
ret = zynqmp_clock_get_parents(i, clock[i].parent,
|
|
&clock[i].num_parents);
|
|
if (ret)
|
|
continue;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_clk_setup() - Setup the clock framework and register clocks
|
|
* @np: Device node
|
|
*
|
|
* Return: 0 on success else error code
|
|
*/
|
|
static int zynqmp_clk_setup(struct device_node *np)
|
|
{
|
|
int ret;
|
|
|
|
ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx),
|
|
GFP_KERNEL);
|
|
if (!zynqmp_data)
|
|
return -ENOMEM;
|
|
|
|
clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
|
|
if (!clock) {
|
|
kfree(zynqmp_data);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
zynqmp_get_clock_info();
|
|
zynqmp_register_clocks(np);
|
|
|
|
zynqmp_data->num = clock_max_idx;
|
|
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
|
|
}
|
|
|
|
static int zynqmp_clock_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
ret = zynqmp_clk_setup(dev->of_node);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id zynqmp_clock_of_match[] = {
|
|
{.compatible = "xlnx,zynqmp-clk"},
|
|
{.compatible = "xlnx,versal-clk"},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
|
|
|
|
static struct platform_driver zynqmp_clock_driver = {
|
|
.driver = {
|
|
.name = "zynqmp_clock",
|
|
.of_match_table = zynqmp_clock_of_match,
|
|
},
|
|
.probe = zynqmp_clock_probe,
|
|
};
|
|
module_platform_driver(zynqmp_clock_driver);
|