Aya Levin a08b4ed137 net/mlx5: Add support to ext_* fields introduced in Port Type and Speed register ... This patch exposes new link modes (including 50Gbps per lane), and ext_* fields which describes the new link modes in Port Type and Speed register (PTYS). Access functions, translation functions (speed <-> HW bits) and link max speed function were modified. Signed-off-by: Aya Levin <ayal@mellanox.com> Reviewed-by: Eran Ben Elisha <eranbe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>		2019-02-14 12:14:42 -08:00
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core	4.21 merge window 2nd pull request	2019-01-05 18:20:51 -08:00
hw	net/mlx5: Add support to ext_* fields introduced in Port Type and Speed register	2019-02-14 12:14:42 -08:00
sw	IB/rxe: Reuse code which sets port state	2018-12-20 14:20:58 -07:00
ulp	IB/ipoib: drop useless LIST_HEAD	2019-01-02 15:42:43 -07:00
Kconfig	RDMA: Fix building with CONFIG_MMU=n	2018-10-03 16:01:03 -06:00
Makefile