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![Chris Wilson](/assets/img/avatar_default.png)
The aliasing_ppgtt provides a PIN_USER alias for the global gtt, so move it under the i915_ggtt to simplify later transformations to enable intel_context.vm. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730143209.4549-1-chris@chris-wilson.co.uk
619 lines
18 KiB
C
619 lines
18 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Please try to maintain the following order within this file unless it makes
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* sense to do otherwise. From top to bottom:
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* 1. typedefs
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* 2. #defines, and macros
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* 3. structure definitions
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* 4. function prototypes
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*
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* Within each section, please try to order by generation in ascending order,
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* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
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*/
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#ifndef __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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#include <linux/io-mapping.h>
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#include <linux/kref.h>
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#include <linux/mm.h>
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#include <linux/pagevec.h>
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#include <linux/workqueue.h>
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#include <drm/drm_mm.h>
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#include "gt/intel_reset.h"
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#include "i915_gem_fence_reg.h"
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#include "i915_request.h"
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#include "i915_scatterlist.h"
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#include "i915_selftest.h"
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#include "gt/intel_timeline.h"
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#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
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#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
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#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
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#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
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#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
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#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
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#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
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/* 32 fences + sign bit for FENCE_REG_NONE */
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#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_file_private;
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struct drm_i915_gem_object;
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struct i915_vma;
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struct intel_gt;
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typedef u32 gen6_pte_t;
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typedef u64 gen8_pte_t;
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#define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
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/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define GEN6_PTE_VALID (1 << 0)
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#define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
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#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
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#define I915_PDES 512
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#define I915_PDE_MASK (I915_PDES - 1)
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#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
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#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
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#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
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#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
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#define GEN6_PDE_SHIFT 22
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#define GEN6_PDE_VALID (1 << 0)
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#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
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#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
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#define BYT_PTE_WRITEABLE (1 << 1)
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/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
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* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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*/
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#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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(((bits) & 0x8) << (11 - 3)))
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#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
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#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
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#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
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#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
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#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
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#define HSW_PTE_UNCACHED (0)
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#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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/*
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* GEN8 32b style address is defined as a 3 level page table:
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* 31:30 | 29:21 | 20:12 | 11:0
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* PDPE | PDE | PTE | offset
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* The difference as compared to normal x86 3 level page table is the PDPEs are
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* programmed via register.
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*
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* GEN8 48b style address is defined as a 4 level page table:
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* 47:39 | 38:30 | 29:21 | 20:12 | 11:0
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* PML4E | PDPE | PDE | PTE | offset
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*/
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#define GEN8_3LVL_PDPES 4
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#define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
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#define PPAT_CACHED_PDE 0 /* WB LLC */
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#define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
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#define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
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#define CHV_PPAT_SNOOP (1<<6)
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#define GEN8_PPAT_AGE(x) ((x)<<4)
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#define GEN8_PPAT_LLCeLLC (3<<2)
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#define GEN8_PPAT_LLCELLC (2<<2)
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#define GEN8_PPAT_LLC (1<<2)
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#define GEN8_PPAT_WB (3<<0)
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#define GEN8_PPAT_WT (2<<0)
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#define GEN8_PPAT_WC (1<<0)
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#define GEN8_PPAT_UC (0<<0)
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#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
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#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
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#define GEN8_PDE_IPS_64K BIT(11)
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#define GEN8_PDE_PS_2M BIT(7)
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#define for_each_sgt_dma(__dmap, __iter, __sgt) \
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__for_each_sgt_dma(__dmap, __iter, __sgt, I915_GTT_PAGE_SIZE)
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struct intel_remapped_plane_info {
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/* in gtt pages */
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unsigned int width, height, stride, offset;
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} __packed;
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struct intel_remapped_info {
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struct intel_remapped_plane_info plane[2];
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unsigned int unused_mbz;
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} __packed;
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struct intel_rotation_info {
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struct intel_remapped_plane_info plane[2];
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} __packed;
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struct intel_partial_info {
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u64 offset;
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unsigned int size;
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} __packed;
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enum i915_ggtt_view_type {
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I915_GGTT_VIEW_NORMAL = 0,
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I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
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I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
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I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
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};
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static inline void assert_i915_gem_gtt_types(void)
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{
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BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
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BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
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BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
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/* Check that rotation/remapped shares offsets for simplicity */
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BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
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offsetof(struct intel_rotation_info, plane[0]));
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BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
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offsetofend(struct intel_rotation_info, plane[1]));
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/* As we encode the size of each branch inside the union into its type,
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* we have to be careful that each branch has a unique size.
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*/
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switch ((enum i915_ggtt_view_type)0) {
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case I915_GGTT_VIEW_NORMAL:
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case I915_GGTT_VIEW_PARTIAL:
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case I915_GGTT_VIEW_ROTATED:
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case I915_GGTT_VIEW_REMAPPED:
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/* gcc complains if these are identical cases */
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break;
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}
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}
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struct i915_ggtt_view {
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enum i915_ggtt_view_type type;
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union {
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/* Members need to contain no holes/padding */
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struct intel_partial_info partial;
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struct intel_rotation_info rotated;
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struct intel_remapped_info remapped;
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};
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};
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enum i915_cache_level;
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struct i915_vma;
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struct i915_page_dma {
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struct page *page;
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union {
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dma_addr_t daddr;
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/* For gen6/gen7 only. This is the offset in the GGTT
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* where the page directory entries for PPGTT begin
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*/
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u32 ggtt_offset;
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};
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};
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struct i915_page_scratch {
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struct i915_page_dma base;
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u64 encode;
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};
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struct i915_page_table {
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struct i915_page_dma base;
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atomic_t used;
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};
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struct i915_page_directory {
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struct i915_page_table pt;
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spinlock_t lock;
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void *entry[512];
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};
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#define __px_choose_expr(x, type, expr, other) \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(x), type) || \
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__builtin_types_compatible_p(typeof(x), const type), \
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({ type __x = (type)(x); expr; }), \
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other)
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#define px_base(px) \
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__px_choose_expr(px, struct i915_page_dma *, __x, \
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__px_choose_expr(px, struct i915_page_scratch *, &__x->base, \
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__px_choose_expr(px, struct i915_page_table *, &__x->base, \
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__px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \
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(void)0))))
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#define px_dma(px) (px_base(px)->daddr)
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#define px_pt(px) \
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__px_choose_expr(px, struct i915_page_table *, __x, \
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__px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
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(void)0))
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#define px_used(px) (&px_pt(px)->used)
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struct i915_vma_ops {
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/* Map an object into an address space with the given cache flags. */
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int (*bind_vma)(struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags);
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/*
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* Unmap an object from an address space. This usually consists of
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* setting the valid PTE entries to a reserved scratch page.
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*/
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void (*unbind_vma)(struct i915_vma *vma);
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int (*set_pages)(struct i915_vma *vma);
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void (*clear_pages)(struct i915_vma *vma);
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};
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struct pagestash {
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spinlock_t lock;
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struct pagevec pvec;
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};
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struct i915_address_space {
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struct kref ref;
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struct rcu_work rcu;
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struct drm_mm mm;
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struct intel_gt *gt;
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struct drm_i915_private *i915;
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struct device *dma;
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/* Every address space belongs to a struct file - except for the global
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* GTT that is owned by the driver (and so @file is set to NULL). In
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* principle, no information should leak from one context to another
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* (or between files/processes etc) unless explicitly shared by the
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* owner. Tracking the owner is important in order to free up per-file
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* objects along with the file, to aide resource tracking, and to
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* assign blame.
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*/
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struct drm_i915_file_private *file;
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u64 total; /* size addr space maps (ex. 2GB for ggtt) */
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u64 reserved; /* size addr space reserved */
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bool closed;
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struct mutex mutex; /* protects vma and our lists */
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#define VM_CLASS_GGTT 0
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#define VM_CLASS_PPGTT 1
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struct i915_page_scratch scratch[4];
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unsigned int scratch_order;
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unsigned int top;
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/**
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* List of vma currently bound.
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*/
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struct list_head bound_list;
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/**
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* List of vma that are not unbound.
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*/
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struct list_head unbound_list;
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struct pagestash free_pages;
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/* Global GTT */
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bool is_ggtt:1;
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/* Some systems require uncached updates of the page directories */
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bool pt_kmap_wc:1;
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/* Some systems support read-only mappings for GGTT and/or PPGTT */
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bool has_read_only:1;
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u64 (*pte_encode)(dma_addr_t addr,
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enum i915_cache_level level,
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u32 flags); /* Create a valid PTE */
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#define PTE_READ_ONLY (1<<0)
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int (*allocate_va_range)(struct i915_address_space *vm,
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u64 start, u64 length);
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void (*clear_range)(struct i915_address_space *vm,
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u64 start, u64 length);
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void (*insert_page)(struct i915_address_space *vm,
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dma_addr_t addr,
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u64 offset,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*insert_entries)(struct i915_address_space *vm,
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struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*cleanup)(struct i915_address_space *vm);
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struct i915_vma_ops vma_ops;
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I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
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I915_SELFTEST_DECLARE(bool scrub_64K);
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};
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#define i915_is_ggtt(vm) ((vm)->is_ggtt)
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static inline bool
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i915_vm_is_4lvl(const struct i915_address_space *vm)
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{
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return (vm->total - 1) >> 32;
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}
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static inline bool
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i915_vm_has_scratch_64K(struct i915_address_space *vm)
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{
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return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
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}
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/* The Graphics Translation Table is the way in which GEN hardware translates a
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* Graphics Virtual Address into a Physical Address. In addition to the normal
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* collateral associated with any va->pa translations GEN hardware also has a
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* portion of the GTT which can be mapped by the CPU and remain both coherent
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* and correct (in cases like swizzling). That region is referred to as GMADR in
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* the spec.
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*/
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struct i915_ggtt {
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struct i915_address_space vm;
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struct io_mapping iomap; /* Mapping to our CPU mappable region */
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struct resource gmadr; /* GMADR resource */
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resource_size_t mappable_end; /* End offset that we can CPU map */
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/** "Graphics Stolen Memory" holds the global PTEs */
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void __iomem *gsm;
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void (*invalidate)(struct i915_ggtt *ggtt);
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/** PPGTT used for aliasing the PPGTT with the GTT */
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struct i915_ppgtt *alias;
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bool do_idle_maps;
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int mtrr;
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u32 pin_bias;
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unsigned int num_fences;
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struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
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struct list_head fence_list;
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/** List of all objects in gtt_space, currently mmaped by userspace.
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* All objects within this list must also be on bound_list.
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*/
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struct list_head userfault_list;
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/* Manual runtime pm autosuspend delay for user GGTT mmaps */
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struct intel_wakeref_auto userfault_wakeref;
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struct drm_mm_node error_capture;
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struct drm_mm_node uc_fw;
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};
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struct i915_ppgtt {
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struct i915_address_space vm;
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intel_engine_mask_t pd_dirty_engines;
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struct i915_page_directory *pd;
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};
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struct gen6_ppgtt {
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struct i915_ppgtt base;
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struct i915_vma *vma;
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gen6_pte_t __iomem *pd_addr;
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unsigned int pin_count;
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bool scan_for_unused_pt;
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};
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#define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base)
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static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base)
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{
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BUILD_BUG_ON(offsetof(struct gen6_ppgtt, base));
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return __to_gen6_ppgtt(base);
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}
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/*
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* gen6_for_each_pde() iterates over every pde from start until start+length.
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* If start and start+length are not perfectly divisible, the macro will round
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* down and up as needed. Start=0 and length=2G effectively iterates over
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* every PDE in the system. The macro modifies ALL its parameters except 'pd',
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* so each of the other parameters should preferably be a simple variable, or
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* at most an lvalue with no side-effects!
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*/
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#define gen6_for_each_pde(pt, pd, start, length, iter) \
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for (iter = gen6_pde_index(start); \
|
|
length > 0 && iter < I915_PDES && \
|
|
(pt = i915_pt_entry(pd, iter), true); \
|
|
({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen6_for_all_pdes(pt, pd, iter) \
|
|
for (iter = 0; \
|
|
iter < I915_PDES && \
|
|
(pt = i915_pt_entry(pd, iter), true); \
|
|
++iter)
|
|
|
|
static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
|
|
{
|
|
const u32 mask = NUM_PTE(pde_shift) - 1;
|
|
|
|
return (address >> PAGE_SHIFT) & mask;
|
|
}
|
|
|
|
/* Helper to counts the number of PTEs within the given length. This count
|
|
* does not cross a page table boundary, so the max value would be
|
|
* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
|
|
*/
|
|
static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
|
|
{
|
|
const u64 mask = ~((1ULL << pde_shift) - 1);
|
|
u64 end;
|
|
|
|
GEM_BUG_ON(length == 0);
|
|
GEM_BUG_ON(offset_in_page(addr | length));
|
|
|
|
end = addr + length;
|
|
|
|
if ((addr & mask) != (end & mask))
|
|
return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
|
|
|
|
return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
|
|
}
|
|
|
|
static inline u32 i915_pde_index(u64 addr, u32 shift)
|
|
{
|
|
return (addr >> shift) & I915_PDE_MASK;
|
|
}
|
|
|
|
static inline u32 gen6_pte_index(u32 addr)
|
|
{
|
|
return i915_pte_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen6_pte_count(u32 addr, u32 length)
|
|
{
|
|
return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen6_pde_index(u32 addr)
|
|
{
|
|
return i915_pde_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline struct i915_page_table *
|
|
i915_pt_entry(const struct i915_page_directory * const pd,
|
|
const unsigned short n)
|
|
{
|
|
return pd->entry[n];
|
|
}
|
|
|
|
static inline struct i915_page_directory *
|
|
i915_pd_entry(const struct i915_page_directory * const pdp,
|
|
const unsigned short n)
|
|
{
|
|
return pdp->entry[n];
|
|
}
|
|
|
|
static inline dma_addr_t
|
|
i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
|
|
{
|
|
struct i915_page_dma *pt = ppgtt->pd->entry[n];
|
|
|
|
return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top]));
|
|
}
|
|
|
|
static inline struct i915_ggtt *
|
|
i915_vm_to_ggtt(struct i915_address_space *vm)
|
|
{
|
|
BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
|
|
GEM_BUG_ON(!i915_is_ggtt(vm));
|
|
return container_of(vm, struct i915_ggtt, vm);
|
|
}
|
|
|
|
static inline struct i915_ppgtt *
|
|
i915_vm_to_ppgtt(struct i915_address_space *vm)
|
|
{
|
|
BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
|
|
GEM_BUG_ON(i915_is_ggtt(vm));
|
|
return container_of(vm, struct i915_ppgtt, vm);
|
|
}
|
|
|
|
int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
|
|
int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
|
|
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
|
|
void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
|
|
void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
|
|
int i915_init_ggtt(struct drm_i915_private *dev_priv);
|
|
void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
|
|
|
|
int i915_ppgtt_init_hw(struct intel_gt *gt);
|
|
|
|
struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
|
|
|
|
static inline struct i915_address_space *
|
|
i915_vm_get(struct i915_address_space *vm)
|
|
{
|
|
kref_get(&vm->ref);
|
|
return vm;
|
|
}
|
|
|
|
void i915_vm_release(struct kref *kref);
|
|
|
|
static inline void i915_vm_put(struct i915_address_space *vm)
|
|
{
|
|
kref_put(&vm->ref, i915_vm_release);
|
|
}
|
|
|
|
int gen6_ppgtt_pin(struct i915_ppgtt *base);
|
|
void gen6_ppgtt_unpin(struct i915_ppgtt *base);
|
|
void gen6_ppgtt_unpin_all(struct i915_ppgtt *base);
|
|
|
|
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
|
|
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
|
|
|
|
int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
|
|
struct sg_table *pages);
|
|
void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
|
|
struct sg_table *pages);
|
|
|
|
int i915_gem_gtt_reserve(struct i915_address_space *vm,
|
|
struct drm_mm_node *node,
|
|
u64 size, u64 offset, unsigned long color,
|
|
unsigned int flags);
|
|
|
|
int i915_gem_gtt_insert(struct i915_address_space *vm,
|
|
struct drm_mm_node *node,
|
|
u64 size, u64 alignment, unsigned long color,
|
|
u64 start, u64 end, unsigned int flags);
|
|
|
|
/* Flags used by pin/bind&friends. */
|
|
#define PIN_NONBLOCK BIT_ULL(0)
|
|
#define PIN_NONFAULT BIT_ULL(1)
|
|
#define PIN_NOEVICT BIT_ULL(2)
|
|
#define PIN_MAPPABLE BIT_ULL(3)
|
|
#define PIN_ZONE_4G BIT_ULL(4)
|
|
#define PIN_HIGH BIT_ULL(5)
|
|
#define PIN_OFFSET_BIAS BIT_ULL(6)
|
|
#define PIN_OFFSET_FIXED BIT_ULL(7)
|
|
|
|
#define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
|
|
#define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
|
|
#define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
|
|
#define PIN_UPDATE BIT_ULL(11)
|
|
|
|
#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
|
|
|
|
#endif
|