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![Michel Thierry](/assets/img/avatar_default.png)
Until Icelake, each engine had its own set of 64 MOCS registers. In order to simplify, Tigerlake moves to only 64 Global MOCS registers, which are no longer part of the engine context. Since these registers are now global, they also only need to be initialized once. >From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU management (5:4) fields and cannot be programmed to 'use the value from Private PAT', because these fields are no longer part of the PPAT. Also cacheability control (1:0) field has changed, 00 no longer means 'use controls from page table', but uncacheable (UC). v2 (Lucas): - Move the changes to the fault registers to a separate commit - the old ones overlap with the range used by the new global MOCS (requested by Daniele) v3 (Lucas): - Clarify comment about setting the unused entries to the same value of index 0, that is the invalid entry (requested by Daniele) - Move changes to DONE_REG and ERROR_GEN6 to a separate commit (requested by Daniele) Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Tomasz Lis <tomasz.lis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730180407.5993-5-lucas.demarchi@intel.com
239 lines
6 KiB
C
239 lines
6 KiB
C
/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DEVICE_INFO_H_
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#define _INTEL_DEVICE_INFO_H_
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#include <uapi/drm/i915_drm.h>
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#include "display/intel_display.h"
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#include "gt/intel_engine_types.h"
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#include "gt/intel_context_types.h"
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#include "gt/intel_sseu.h"
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struct drm_printer;
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struct drm_i915_private;
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/* Keep in gen based order, and chronological order within a gen */
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enum intel_platform {
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INTEL_PLATFORM_UNINITIALIZED = 0,
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/* gen2 */
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INTEL_I830,
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INTEL_I845G,
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INTEL_I85X,
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INTEL_I865G,
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/* gen3 */
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INTEL_I915G,
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INTEL_I915GM,
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INTEL_I945G,
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INTEL_I945GM,
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INTEL_G33,
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INTEL_PINEVIEW,
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/* gen4 */
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INTEL_I965G,
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INTEL_I965GM,
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INTEL_G45,
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INTEL_GM45,
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/* gen5 */
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INTEL_IRONLAKE,
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/* gen6 */
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INTEL_SANDYBRIDGE,
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/* gen7 */
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INTEL_IVYBRIDGE,
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INTEL_VALLEYVIEW,
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INTEL_HASWELL,
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/* gen8 */
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INTEL_BROADWELL,
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INTEL_CHERRYVIEW,
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/* gen9 */
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INTEL_SKYLAKE,
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INTEL_BROXTON,
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INTEL_KABYLAKE,
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INTEL_GEMINILAKE,
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INTEL_COFFEELAKE,
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/* gen10 */
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INTEL_CANNONLAKE,
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/* gen11 */
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INTEL_ICELAKE,
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INTEL_ELKHARTLAKE,
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/* gen12 */
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INTEL_TIGERLAKE,
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INTEL_MAX_PLATFORMS
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};
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/*
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* Subplatform bits share the same namespace per parent platform. In other words
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* it is fine for the same bit to be used on multiple parent platforms.
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*/
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#define INTEL_SUBPLATFORM_BITS (3)
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/* HSW/BDW/SKL/KBL/CFL */
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#define INTEL_SUBPLATFORM_ULT (0)
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#define INTEL_SUBPLATFORM_ULX (1)
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/* CNL/ICL */
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#define INTEL_SUBPLATFORM_PORTF (0)
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enum intel_ppgtt_type {
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INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
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INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
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INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
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};
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#define DEV_INFO_FOR_EACH_FLAG(func) \
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func(is_mobile); \
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func(is_lp); \
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func(require_force_probe); \
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/* Keep has_* in alphabetical order */ \
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func(has_64bit_reloc); \
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func(gpu_reset_clobbers_display); \
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func(has_reset_engine); \
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func(has_fpga_dbg); \
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func(has_global_mocs); \
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func(has_gt_uc); \
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func(has_l3_dpf); \
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func(has_llc); \
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func(has_logical_ring_contexts); \
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func(has_logical_ring_elsq); \
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func(has_logical_ring_preemption); \
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func(has_pooled_eu); \
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func(has_rc6); \
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func(has_rc6p); \
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func(has_rps); \
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func(has_runtime_pm); \
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func(has_snoop); \
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func(has_coherent_ggtt); \
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func(unfenced_needs_alignment); \
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func(hws_needs_physical);
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#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
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/* Keep in alphabetical order */ \
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func(cursor_needs_physical); \
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func(has_csr); \
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func(has_ddi); \
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func(has_dp_mst); \
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func(has_fbc); \
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func(has_gmch); \
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func(has_hotplug); \
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func(has_ipc); \
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func(has_modular_fia); \
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func(has_overlay); \
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func(has_psr); \
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func(overlay_needs_physical); \
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func(supports_tv);
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struct intel_device_info {
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u16 gen_mask;
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u8 gen;
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u8 gt; /* GT number, 0 if undefined */
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intel_engine_mask_t engine_mask; /* Engines supported by the HW */
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enum intel_platform platform;
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enum intel_ppgtt_type ppgtt_type;
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unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
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unsigned int page_sizes; /* page sizes supported by the HW */
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u32 display_mmio_offset;
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u8 num_pipes;
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#define DEFINE_FLAG(name) u8 name:1
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DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
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#undef DEFINE_FLAG
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struct {
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#define DEFINE_FLAG(name) u8 name:1
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DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
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#undef DEFINE_FLAG
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} display;
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u16 ddb_size; /* in blocks */
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/* Register offsets for the various display pipes and transcoders */
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int pipe_offsets[I915_MAX_TRANSCODERS];
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int trans_offsets[I915_MAX_TRANSCODERS];
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int cursor_offsets[I915_MAX_PIPES];
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struct color_luts {
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u32 degamma_lut_size;
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u32 gamma_lut_size;
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u32 degamma_lut_tests;
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u32 gamma_lut_tests;
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} color;
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};
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struct intel_runtime_info {
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/*
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* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
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* into single runtime conditionals, and also to provide groundwork
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* for future per platform, or per SKU build optimizations.
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*
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* Array can be extended when necessary if the corresponding
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* BUILD_BUG_ON is hit.
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*/
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u32 platform_mask[2];
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u16 device_id;
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u8 num_sprites[I915_MAX_PIPES];
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u8 num_scalers[I915_MAX_PIPES];
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u8 num_engines;
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/* Slice/subslice/EU info */
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struct sseu_dev_info sseu;
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u32 cs_timestamp_frequency_khz;
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/* Media engine access to SFC per instance */
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u8 vdbox_sfc_access;
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};
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struct intel_driver_caps {
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unsigned int scheduler;
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bool has_logical_contexts:1;
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};
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const char *intel_platform_name(enum intel_platform platform);
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void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
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void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
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void intel_device_info_dump_flags(const struct intel_device_info *info,
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struct drm_printer *p);
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void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
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struct drm_printer *p);
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void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
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struct drm_printer *p);
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void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
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void intel_driver_caps_print(const struct intel_driver_caps *caps,
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struct drm_printer *p);
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#endif
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