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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
483 lines
13 KiB
C
483 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#define MIPITX_DSI_CON 0x00
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#define RG_DSI_LDOCORE_EN BIT(0)
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#define RG_DSI_CKG_LDOOUT_EN BIT(1)
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#define RG_DSI_BCLK_SEL (3 << 2)
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#define RG_DSI_LD_IDX_SEL (7 << 4)
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#define RG_DSI_PHYCLK_SEL (2 << 8)
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#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
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#define RG_DSI_LPTX_CLMP_EN BIT(11)
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#define MIPITX_DSI_CLOCK_LANE 0x04
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#define MIPITX_DSI_DATA_LANE0 0x08
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#define MIPITX_DSI_DATA_LANE1 0x0c
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#define MIPITX_DSI_DATA_LANE2 0x10
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#define MIPITX_DSI_DATA_LANE3 0x14
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#define RG_DSI_LNTx_LDOOUT_EN BIT(0)
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#define RG_DSI_LNTx_CKLANE_EN BIT(1)
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#define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
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#define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
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#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
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#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
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#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
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#define RG_DSI_LNTx_RT_CODE (0xf << 8)
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#define MIPITX_DSI_TOP_CON 0x40
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#define RG_DSI_LNT_INTR_EN BIT(0)
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#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
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#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
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#define RG_DSI_LNT_TESTMODE_EN BIT(3)
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#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
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#define RG_DSI_LNT_AIO_SEL (7 << 8)
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#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
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#define RG_DSI_DEBUG_INPUT_EN BIT(12)
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#define RG_DSI_PRESERVE (7 << 13)
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#define MIPITX_DSI_BG_CON 0x44
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#define RG_DSI_BG_CORE_EN BIT(0)
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#define RG_DSI_BG_CKEN BIT(1)
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#define RG_DSI_BG_DIV (0x3 << 2)
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#define RG_DSI_BG_FAST_CHARGE BIT(4)
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#define RG_DSI_VOUT_MSK (0x3ffff << 5)
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#define RG_DSI_V12_SEL (7 << 5)
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#define RG_DSI_V10_SEL (7 << 8)
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#define RG_DSI_V072_SEL (7 << 11)
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#define RG_DSI_V04_SEL (7 << 14)
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#define RG_DSI_V032_SEL (7 << 17)
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#define RG_DSI_V02_SEL (7 << 20)
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#define RG_DSI_BG_R1_TRIM (0xf << 24)
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#define RG_DSI_BG_R2_TRIM (0xf << 28)
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#define MIPITX_DSI_PLL_CON0 0x50
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#define RG_DSI_MPPLL_PLL_EN BIT(0)
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#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
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#define RG_DSI_MPPLL_PREDIV (3 << 1)
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#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
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#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
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#define RG_DSI_MPPLL_POSDIV (7 << 7)
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#define RG_DSI_MPPLL_MONVC_EN BIT(10)
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#define RG_DSI_MPPLL_MONREF_EN BIT(11)
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#define RG_DSI_MPPLL_VOD_EN BIT(12)
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#define MIPITX_DSI_PLL_CON1 0x54
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#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
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#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
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#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
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#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
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#define MIPITX_DSI_PLL_CON2 0x58
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#define MIPITX_DSI_PLL_TOP 0x64
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#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
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#define MIPITX_DSI_PLL_PWR 0x68
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#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
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#define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
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#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
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#define MIPITX_DSI_SW_CTRL 0x80
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#define SW_CTRL_EN BIT(0)
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#define MIPITX_DSI_SW_CTRL_CON0 0x84
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#define SW_LNTC_LPTX_PRE_OE BIT(0)
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#define SW_LNTC_LPTX_OE BIT(1)
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#define SW_LNTC_LPTX_P BIT(2)
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#define SW_LNTC_LPTX_N BIT(3)
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#define SW_LNTC_HSTX_PRE_OE BIT(4)
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#define SW_LNTC_HSTX_OE BIT(5)
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#define SW_LNTC_HSTX_ZEROCLK BIT(6)
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#define SW_LNT0_LPTX_PRE_OE BIT(7)
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#define SW_LNT0_LPTX_OE BIT(8)
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#define SW_LNT0_LPTX_P BIT(9)
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#define SW_LNT0_LPTX_N BIT(10)
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#define SW_LNT0_HSTX_PRE_OE BIT(11)
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#define SW_LNT0_HSTX_OE BIT(12)
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#define SW_LNT0_LPRX_EN BIT(13)
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#define SW_LNT1_LPTX_PRE_OE BIT(14)
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#define SW_LNT1_LPTX_OE BIT(15)
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#define SW_LNT1_LPTX_P BIT(16)
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#define SW_LNT1_LPTX_N BIT(17)
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#define SW_LNT1_HSTX_PRE_OE BIT(18)
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#define SW_LNT1_HSTX_OE BIT(19)
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#define SW_LNT2_LPTX_PRE_OE BIT(20)
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#define SW_LNT2_LPTX_OE BIT(21)
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#define SW_LNT2_LPTX_P BIT(22)
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#define SW_LNT2_LPTX_N BIT(23)
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#define SW_LNT2_HSTX_PRE_OE BIT(24)
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#define SW_LNT2_HSTX_OE BIT(25)
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struct mtk_mipitx_data {
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const u32 mppll_preserve;
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};
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struct mtk_mipi_tx {
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struct device *dev;
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void __iomem *regs;
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u32 data_rate;
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const struct mtk_mipitx_data *driver_data;
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struct clk_hw pll_hw;
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struct clk *pll;
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};
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static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_mipi_tx, pll_hw);
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}
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static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 bits)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel(temp & ~bits, mipi_tx->regs + offset);
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}
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static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 bits)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel(temp | bits, mipi_tx->regs + offset);
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}
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static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 mask, u32 data)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
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}
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static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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u8 txdiv, txdiv0, txdiv1;
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u64 pcw;
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dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
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if (mipi_tx->data_rate >= 500000000) {
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txdiv = 1;
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txdiv0 = 0;
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txdiv1 = 0;
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} else if (mipi_tx->data_rate >= 250000000) {
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txdiv = 2;
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txdiv0 = 1;
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txdiv1 = 0;
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} else if (mipi_tx->data_rate >= 125000000) {
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txdiv = 4;
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txdiv0 = 2;
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txdiv1 = 0;
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} else if (mipi_tx->data_rate > 62000000) {
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txdiv = 8;
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txdiv0 = 2;
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txdiv1 = 1;
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} else if (mipi_tx->data_rate >= 50000000) {
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txdiv = 16;
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txdiv0 = 2;
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txdiv1 = 2;
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} else {
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return -EINVAL;
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}
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
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RG_DSI_VOUT_MSK |
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
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(4 << 20) | (4 << 17) | (4 << 14) |
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(4 << 11) | (4 << 8) | (4 << 5) |
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
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usleep_range(30, 100);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
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RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
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(8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
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RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
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RG_DSI_MPPLL_SDM_PWR_ON |
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RG_DSI_MPPLL_SDM_ISO_EN,
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RG_DSI_MPPLL_SDM_PWR_ON);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
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RG_DSI_MPPLL_PLL_EN);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
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RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
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RG_DSI_MPPLL_PREDIV,
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(txdiv0 << 3) | (txdiv1 << 5));
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/*
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* PLL PCW config
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* PCW bit 24~30 = integer part of pcw
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* PCW bit 0~23 = fractional part of pcw
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* pcw = data_Rate*4*txdiv/(Ref_clk*2);
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* Post DIV =4, so need data_Rate*4
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* Ref_clk is 26MHz
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*/
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pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
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26000000);
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writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
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RG_DSI_MPPLL_SDM_FRA_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
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usleep_range(20, 100);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
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RG_DSI_MPPLL_SDM_SSC_EN);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
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RG_DSI_MPPLL_PRESERVE,
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mipi_tx->driver_data->mppll_preserve);
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return 0;
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}
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static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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dev_dbg(mipi_tx->dev, "unprepare\n");
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
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RG_DSI_MPPLL_PLL_EN);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
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RG_DSI_MPPLL_PRESERVE, 0);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
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RG_DSI_MPPLL_SDM_ISO_EN |
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RG_DSI_MPPLL_SDM_PWR_ON,
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RG_DSI_MPPLL_SDM_ISO_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
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RG_DSI_LNT_HS_BIAS_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
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RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
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RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
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RG_DSI_MPPLL_DIV_MSK);
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}
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static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return clamp_val(rate, 50000000, 1250000000);
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}
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static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
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mipi_tx->data_rate = rate;
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return 0;
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}
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static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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return mipi_tx->data_rate;
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}
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static const struct clk_ops mtk_mipi_tx_pll_ops = {
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.prepare = mtk_mipi_tx_pll_prepare,
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.unprepare = mtk_mipi_tx_pll_unprepare,
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.round_rate = mtk_mipi_tx_pll_round_rate,
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.set_rate = mtk_mipi_tx_pll_set_rate,
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.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
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};
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static int mtk_mipi_tx_power_on_signal(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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u32 reg;
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for (reg = MIPITX_DSI_CLOCK_LANE;
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reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
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mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
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RG_DSI_PAD_TIE_LOW_EN);
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return 0;
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}
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static int mtk_mipi_tx_power_on(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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int ret;
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/* Power up core and enable PLL */
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ret = clk_prepare_enable(mipi_tx->pll);
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if (ret < 0)
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return ret;
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/* Enable DSI Lane LDO outputs, disable pad tie low */
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mtk_mipi_tx_power_on_signal(phy);
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return 0;
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}
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static void mtk_mipi_tx_power_off_signal(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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u32 reg;
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
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RG_DSI_PAD_TIE_LOW_EN);
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for (reg = MIPITX_DSI_CLOCK_LANE;
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reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
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mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
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}
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static int mtk_mipi_tx_power_off(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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/* Enable pad tie low, disable DSI Lane LDO outputs */
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mtk_mipi_tx_power_off_signal(phy);
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/* Disable PLL and power down core */
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clk_disable_unprepare(mipi_tx->pll);
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return 0;
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}
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static const struct phy_ops mtk_mipi_tx_ops = {
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.power_on = mtk_mipi_tx_power_on,
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.power_off = mtk_mipi_tx_power_off,
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.owner = THIS_MODULE,
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};
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static int mtk_mipi_tx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_mipi_tx *mipi_tx;
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struct resource *mem;
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struct clk *ref_clk;
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const char *ref_clk_name;
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struct clk_init_data clk_init = {
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.ops = &mtk_mipi_tx_pll_ops,
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.num_parents = 1,
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.parent_names = (const char * const *)&ref_clk_name,
|
|
.flags = CLK_SET_RATE_GATE,
|
|
};
|
|
struct phy *phy;
|
|
struct phy_provider *phy_provider;
|
|
int ret;
|
|
|
|
mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
|
|
if (!mipi_tx)
|
|
return -ENOMEM;
|
|
|
|
mipi_tx->driver_data = of_device_get_match_data(dev);
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
mipi_tx->regs = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(mipi_tx->regs)) {
|
|
ret = PTR_ERR(mipi_tx->regs);
|
|
dev_err(dev, "Failed to get memory resource: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ref_clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(ref_clk)) {
|
|
ret = PTR_ERR(ref_clk);
|
|
dev_err(dev, "Failed to get reference clock: %d\n", ret);
|
|
return ret;
|
|
}
|
|
ref_clk_name = __clk_get_name(ref_clk);
|
|
|
|
ret = of_property_read_string(dev->of_node, "clock-output-names",
|
|
&clk_init.name);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
mipi_tx->pll_hw.init = &clk_init;
|
|
mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
|
|
if (IS_ERR(mipi_tx->pll)) {
|
|
ret = PTR_ERR(mipi_tx->pll);
|
|
dev_err(dev, "Failed to register PLL: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
|
|
if (IS_ERR(phy)) {
|
|
ret = PTR_ERR(phy);
|
|
dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
|
|
return ret;
|
|
}
|
|
phy_set_drvdata(phy, mipi_tx);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (IS_ERR(phy_provider)) {
|
|
ret = PTR_ERR(phy_provider);
|
|
return ret;
|
|
}
|
|
|
|
mipi_tx->dev = dev;
|
|
|
|
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
|
|
mipi_tx->pll);
|
|
}
|
|
|
|
static int mtk_mipi_tx_remove(struct platform_device *pdev)
|
|
{
|
|
of_clk_del_provider(pdev->dev.of_node);
|
|
return 0;
|
|
}
|
|
|
|
static const struct mtk_mipitx_data mt2701_mipitx_data = {
|
|
.mppll_preserve = (3 << 8)
|
|
};
|
|
|
|
static const struct mtk_mipitx_data mt8173_mipitx_data = {
|
|
.mppll_preserve = (0 << 8)
|
|
};
|
|
|
|
static const struct of_device_id mtk_mipi_tx_match[] = {
|
|
{ .compatible = "mediatek,mt2701-mipi-tx",
|
|
.data = &mt2701_mipitx_data },
|
|
{ .compatible = "mediatek,mt8173-mipi-tx",
|
|
.data = &mt8173_mipitx_data },
|
|
{},
|
|
};
|
|
|
|
struct platform_driver mtk_mipi_tx_driver = {
|
|
.probe = mtk_mipi_tx_probe,
|
|
.remove = mtk_mipi_tx_remove,
|
|
.driver = {
|
|
.name = "mediatek-mipi-tx",
|
|
.of_match_table = mtk_mipi_tx_match,
|
|
},
|
|
};
|