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![Shunli Wang](/assets/img/avatar_default.png)
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
238 lines
5.6 KiB
C
238 lines
5.6 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRV_CLK_MTK_H
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#define __DRV_CLK_MTK_H
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#include <linux/regmap.h>
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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struct clk;
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#define MAX_MUX_GATE_BIT 31
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#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
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#define MHZ (1000 * 1000)
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struct mtk_fixed_clk {
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int id;
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const char *name;
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const char *parent;
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unsigned long rate;
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};
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#define FIXED_CLK(_id, _name, _parent, _rate) { \
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.id = _id, \
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.name = _name, \
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.parent = _parent, \
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.rate = _rate, \
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}
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void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
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int num, struct clk_onecell_data *clk_data);
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struct mtk_fixed_factor {
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int id;
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const char *name;
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const char *parent_name;
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int mult;
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int div;
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};
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#define FACTOR(_id, _name, _parent, _mult, _div) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.mult = _mult, \
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.div = _div, \
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}
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void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
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int num, struct clk_onecell_data *clk_data);
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struct mtk_composite {
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int id;
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const char *name;
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const char * const *parent_names;
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const char *parent;
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unsigned flags;
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uint32_t mux_reg;
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uint32_t divider_reg;
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uint32_t gate_reg;
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signed char mux_shift;
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signed char mux_width;
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signed char gate_shift;
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signed char divider_shift;
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signed char divider_width;
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signed char num_parents;
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};
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/*
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* In case the rate change propagation to parent clocks is undesirable,
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* this macro allows to specify the clock flags manually.
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*/
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#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
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_gate, _flags) { \
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.id = _id, \
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.name = _name, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_reg = _reg, \
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.gate_shift = _gate, \
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.divider_shift = -1, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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}
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/*
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* Unless necessary, all MUX_GATE clocks propagate rate changes to their
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* parent clock by default.
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*/
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#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
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MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
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_gate, CLK_SET_RATE_PARENT)
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#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
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.id = _id, \
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.name = _name, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = -1, \
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.divider_shift = -1, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = CLK_SET_RATE_PARENT, \
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}
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#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
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_div_width, _div_shift) { \
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.id = _id, \
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.parent = _parent, \
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.name = _name, \
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.divider_reg = _div_reg, \
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.divider_shift = _div_shift, \
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.divider_width = _div_width, \
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.gate_reg = _gate_reg, \
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.gate_shift = _gate_shift, \
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.mux_shift = -1, \
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.flags = 0, \
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}
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struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
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void __iomem *base, spinlock_t *lock);
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void mtk_clk_register_composites(const struct mtk_composite *mcs,
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int num, void __iomem *base, spinlock_t *lock,
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struct clk_onecell_data *clk_data);
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struct mtk_gate_regs {
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u32 sta_ofs;
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u32 clr_ofs;
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u32 set_ofs;
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};
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struct mtk_gate {
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int id;
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const char *name;
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const char *parent_name;
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const struct mtk_gate_regs *regs;
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int shift;
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const struct clk_ops *ops;
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};
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int mtk_clk_register_gates(struct device_node *node,
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const struct mtk_gate *clks, int num,
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struct clk_onecell_data *clk_data);
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struct mtk_clk_divider {
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int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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u32 div_reg;
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unsigned char div_shift;
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unsigned char div_width;
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unsigned char clk_divider_flags;
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const struct clk_div_table *clk_div_table;
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};
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#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.div_reg = _reg, \
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.div_shift = _shift, \
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.div_width = _width, \
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}
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void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
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int num, void __iomem *base, spinlock_t *lock,
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struct clk_onecell_data *clk_data);
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struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
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#define HAVE_RST_BAR BIT(0)
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#define PLL_AO BIT(1)
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struct mtk_pll_div_table {
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u32 div;
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unsigned long freq;
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};
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struct mtk_pll_data {
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int id;
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const char *name;
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uint32_t reg;
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uint32_t pwr_reg;
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uint32_t en_mask;
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uint32_t pd_reg;
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uint32_t tuner_reg;
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int pd_shift;
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unsigned int flags;
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const struct clk_ops *ops;
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u32 rst_bar_mask;
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unsigned long fmax;
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int pcwbits;
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uint32_t pcw_reg;
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int pcw_shift;
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const struct mtk_pll_div_table *div_table;
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};
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void mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_onecell_data *clk_data);
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struct clk *mtk_clk_register_ref2usb_tx(const char *name,
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const char *parent_name, void __iomem *reg);
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#ifdef CONFIG_RESET_CONTROLLER
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void mtk_register_reset_controller(struct device_node *np,
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unsigned int num_regs, int regofs);
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#else
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static inline void mtk_register_reset_controller(struct device_node *np,
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unsigned int num_regs, int regofs)
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{
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}
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#endif
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#endif /* __DRV_CLK_MTK_H */
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