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![Rhyland Klein](/assets/img/avatar_default.png)
tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
225 lines
5.6 KiB
C
225 lines
5.6 KiB
C
/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define AUDIO_SYNC_CLK_I2S0 0x4a0
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#define AUDIO_SYNC_CLK_I2S1 0x4a4
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#define AUDIO_SYNC_CLK_I2S2 0x4a8
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#define AUDIO_SYNC_CLK_I2S3 0x4ac
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#define AUDIO_SYNC_CLK_I2S4 0x4b0
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#define AUDIO_SYNC_CLK_SPDIF 0x4b4
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#define AUDIO_SYNC_DOUBLER 0x49c
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#define PLLA_OUT 0xb4
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struct tegra_sync_source_initdata {
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char *name;
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unsigned long rate;
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unsigned long max_rate;
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int clk_id;
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};
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#define SYNC(_name) \
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{\
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.name = #_name,\
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.rate = 24000000,\
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.max_rate = 24000000,\
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.clk_id = tegra_clk_ ## _name,\
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}
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struct tegra_audio_clk_initdata {
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char *gate_name;
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char *mux_name;
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u32 offset;
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int gate_clk_id;
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int mux_clk_id;
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};
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#define AUDIO(_name, _offset) \
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{\
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.gate_name = #_name,\
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.mux_name = #_name"_mux",\
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.offset = _offset,\
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.gate_clk_id = tegra_clk_ ## _name,\
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.mux_clk_id = tegra_clk_ ## _name ## _mux,\
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}
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struct tegra_audio2x_clk_initdata {
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char *parent;
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char *gate_name;
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char *name_2x;
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char *div_name;
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int clk_id;
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int clk_num;
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u8 div_offset;
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};
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#define AUDIO2X(_name, _num, _offset) \
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{\
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.parent = #_name,\
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.gate_name = #_name"_2x",\
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.name_2x = #_name"_doubler",\
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.div_name = #_name"_div",\
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.clk_id = tegra_clk_ ## _name ## _2x,\
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.clk_num = _num,\
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.div_offset = _offset,\
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}
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static DEFINE_SPINLOCK(clk_doubler_lock);
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static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
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"i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
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};
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static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
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SYNC(spdif_in_sync),
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SYNC(i2s0_sync),
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SYNC(i2s1_sync),
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SYNC(i2s2_sync),
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SYNC(i2s3_sync),
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SYNC(i2s4_sync),
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SYNC(vimclk_sync),
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};
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static struct tegra_audio_clk_initdata audio_clks[] = {
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AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
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AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
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AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
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AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
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AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
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AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
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};
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static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
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AUDIO2X(audio0, 113, 24),
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AUDIO2X(audio1, 114, 25),
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AUDIO2X(audio2, 115, 26),
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AUDIO2X(audio3, 116, 27),
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AUDIO2X(audio4, 117, 28),
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AUDIO2X(spdif, 118, 29),
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};
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void __init tegra_audio_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base, struct tegra_clk *tegra_clks,
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struct tegra_audio_clk_info *audio_info,
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unsigned int num_plls)
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{
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struct clk *clk;
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struct clk **dt_clk;
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int i;
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if (!audio_info || num_plls < 1) {
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pr_err("No audio data passed to tegra_audio_clk_init\n");
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WARN_ON(1);
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return;
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}
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for (i = 0; i < num_plls; i++) {
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struct tegra_audio_clk_info *info = &audio_info[i];
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dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_pll(info->name, info->parent,
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clk_base, pmc_base, 0, info->pll_params,
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NULL);
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*dt_clk = clk;
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}
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}
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/* PLLA_OUT0 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
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clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
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8, 8, 1, NULL);
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clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
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clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
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CLK_SET_RATE_PARENT, 0, NULL);
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*dt_clk = clk;
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}
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for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
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struct tegra_sync_source_initdata *data;
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data = &sync_source_clks[i];
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dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = tegra_clk_register_sync_source(data->name,
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data->rate, data->max_rate);
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*dt_clk = clk;
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}
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for (i = 0; i < ARRAY_SIZE(audio_clks); i++) {
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struct tegra_audio_clk_initdata *data;
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data = &audio_clks[i];
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dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk,
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ARRAY_SIZE(mux_audio_sync_clk),
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CLK_SET_RATE_NO_REPARENT,
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clk_base + data->offset, 0, 3, 0,
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NULL);
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*dt_clk = clk;
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dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
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0, clk_base + data->offset, 4,
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CLK_GATE_SET_TO_DISABLE, NULL);
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*dt_clk = clk;
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}
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for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
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struct tegra_audio2x_clk_initdata *data;
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data = &audio2x_clks[i];
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dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_fixed_factor(NULL, data->name_2x,
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data->parent, CLK_SET_RATE_PARENT, 2, 1);
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clk = tegra_clk_register_divider(data->div_name,
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data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
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0, 0, data->div_offset, 1, 0,
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&clk_doubler_lock);
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clk = tegra_clk_register_periph_gate(data->gate_name,
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data->div_name, TEGRA_PERIPH_NO_RESET,
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clk_base, CLK_SET_RATE_PARENT, data->clk_num,
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periph_clk_enb_refcnt);
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*dt_clk = clk;
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}
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}
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