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![Andrey Ryabinin](/assets/img/avatar_default.png)
pmc_core_mtpmc_link_status() an pmc_core_check_read_lock_bit() use
test_bit() on local 32-bit variable. This causes out-of-bounds
access since test_bit() expects object at least of 'unsigned long' size:
BUG: KASAN: stack-out-of-bounds in pmc_core_probe+0x3aa/0x3b0
Call Trace:
__asan_report_load_n_noabort+0x5c/0x80
pmc_core_probe+0x3aa/0x3b0
local_pci_probe+0xf9/0x1e0
pci_device_probe+0x27b/0x350
driver_probe_device+0x419/0x830
__driver_attach+0x15f/0x1d0
bus_for_each_dev+0x129/0x1d0
driver_attach+0x42/0x70
bus_add_driver+0x385/0x690
driver_register+0x1a9/0x3d0
__pci_register_driver+0x1a2/0x290
intel_pmc_core_driver_init+0x19/0x1b
do_one_initcall+0x12e/0x280
kernel_init_freeable+0x57c/0x623
kernel_init+0x13/0x140
ret_from_fork+0x2e/0x40
Fix this by open coding bit test. While at it, also refactor this code
a little bit.
Fixes: 173943b3da
("platform/x86: intel_pmc_core: ModPhy core lanes pg status")
Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
[andy: reverted not related changes, used BIT() macro]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
550 lines
15 KiB
C
550 lines
15 KiB
C
/*
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* Intel Core SoC Power Management Controller Driver
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*
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* Copyright (c) 2016, Intel Corporation.
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* All Rights Reserved.
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*
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* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/uaccess.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/pmc_core.h>
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#include "intel_pmc_core.h"
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static struct pmc_dev pmc;
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static const struct pmc_bit_map spt_pll_map[] = {
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{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
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{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
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{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
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{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
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{},
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};
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static const struct pmc_bit_map spt_mphy_map[] = {
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{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
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{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
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{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
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{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
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{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
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{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
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{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
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{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
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{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
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{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
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{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
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{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
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{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
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{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
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{},
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};
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static const struct pmc_bit_map spt_pfear_map[] = {
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{"PMC", SPT_PMC_BIT_PMC},
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{"OPI-DMI", SPT_PMC_BIT_OPI},
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{"SPI / eSPI", SPT_PMC_BIT_SPI},
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{"XHCI", SPT_PMC_BIT_XHCI},
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{"SPA", SPT_PMC_BIT_SPA},
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{"SPB", SPT_PMC_BIT_SPB},
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{"SPC", SPT_PMC_BIT_SPC},
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{"GBE", SPT_PMC_BIT_GBE},
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{"SATA", SPT_PMC_BIT_SATA},
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{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
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{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
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{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
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{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
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{"RSVD", SPT_PMC_BIT_RSVD_0B},
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{"LPSS", SPT_PMC_BIT_LPSS},
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{"LPC", SPT_PMC_BIT_LPC},
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{"SMB", SPT_PMC_BIT_SMB},
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{"ISH", SPT_PMC_BIT_ISH},
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{"P2SB", SPT_PMC_BIT_P2SB},
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{"DFX", SPT_PMC_BIT_DFX},
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{"SCC", SPT_PMC_BIT_SCC},
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{"RSVD", SPT_PMC_BIT_RSVD_0C},
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{"FUSE", SPT_PMC_BIT_FUSE},
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{"CAMERA", SPT_PMC_BIT_CAMREA},
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{"RSVD", SPT_PMC_BIT_RSVD_0D},
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{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
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{"EXI", SPT_PMC_BIT_EXI},
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{"CSE", SPT_PMC_BIT_CSE},
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{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
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{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
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{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
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{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
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{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
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{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
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{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
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{"RSVD", SPT_PMC_BIT_RSVD_1A},
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{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
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{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
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{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
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{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
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{},
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};
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static const struct pmc_reg_map spt_reg_map = {
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.pfear_sts = spt_pfear_map,
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.mphy_sts = spt_mphy_map,
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.pll_sts = spt_pll_map,
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};
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static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
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(kernel_ulong_t)&spt_reg_map },
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{ 0, },
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};
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static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
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{
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return readb(pmcdev->regbase + offset);
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}
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static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
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{
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return readl(pmcdev->regbase + reg_offset);
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}
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static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
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reg_offset, u32 val)
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{
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writel(val, pmcdev->regbase + reg_offset);
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}
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static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
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{
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return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
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}
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/**
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* intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
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* @data: Out param that contains current SLP_S0 count.
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*
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* This API currently supports Intel Skylake SoC and Sunrise
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* Point Platform Controller Hub. Future platform support
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* should be added for platforms that support low power modes
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* beyond Package C10 state.
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*
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* SLP_S0_RESIDENCY counter counts in 100 us granularity per
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* step hence function populates the multiplied value in out
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* parameter @data.
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*
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* Return: an error code or 0 on success.
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*/
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int intel_pmc_slp_s0_counter_read(u32 *data)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 value;
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if (!pmcdev->has_slp_s0_res)
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return -EACCES;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
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*data = pmc_core_adjust_slp_s0_step(value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
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static int pmc_core_dev_state_get(void *data, u64 *val)
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{
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struct pmc_dev *pmcdev = data;
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u32 value;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
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*val = pmc_core_adjust_slp_s0_step(value);
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
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static int pmc_core_check_read_lock_bit(void)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 value;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_CFG_OFFSET);
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return value & BIT(SPT_PMC_READ_DISABLE_BIT);
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}
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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static void pmc_core_display_map(struct seq_file *s, int index,
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u8 pf_reg, const struct pmc_bit_map *pf_map)
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{
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seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
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index, pf_map[index].name,
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pf_map[index].bit_mask & pf_reg ? "Off" : "On");
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}
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static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmcdev = s->private;
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const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
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u8 pf_regs[NUM_ENTRIES];
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int index, iter;
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iter = SPT_PMC_XRAM_PPFEAR0A;
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for (index = 0; index < NUM_ENTRIES; index++, iter++)
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pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
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for (index = 0; map[index].name; index++)
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pmc_core_display_map(s, index, pf_regs[index / 8], map);
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return 0;
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}
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static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
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}
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static const struct file_operations pmc_core_ppfear_ops = {
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.open = pmc_core_ppfear_sts_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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/* This function should return link status, 0 means ready */
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static int pmc_core_mtpmc_link_status(void)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 value;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
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return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
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}
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static int pmc_core_send_msg(u32 *addr_xram)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 dest;
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int timeout;
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for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
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if (pmc_core_mtpmc_link_status() == 0)
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break;
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msleep(5);
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}
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if (timeout <= 0 && pmc_core_mtpmc_link_status())
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return -EBUSY;
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dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
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pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
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return 0;
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}
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static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmcdev = s->private;
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const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
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u32 mphy_core_reg_low, mphy_core_reg_high;
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u32 val_low, val_high;
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int index, err = 0;
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if (pmcdev->pmc_xram_read_bit) {
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seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
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return 0;
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}
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mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
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mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
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mutex_lock(&pmcdev->lock);
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if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
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err = -EBUSY;
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goto out_unlock;
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}
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msleep(10);
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val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
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err = -EBUSY;
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goto out_unlock;
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}
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msleep(10);
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val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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for (index = 0; map[index].name && index < 8; index++) {
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seq_printf(s, "%-32s\tState: %s\n",
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map[index].name,
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map[index].bit_mask & val_low ? "Not power gated" :
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"Power gated");
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}
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for (index = 8; map[index].name; index++) {
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seq_printf(s, "%-32s\tState: %s\n",
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map[index].name,
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map[index].bit_mask & val_high ? "Not power gated" :
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"Power gated");
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}
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out_unlock:
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mutex_unlock(&pmcdev->lock);
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return err;
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}
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static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
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}
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static const struct file_operations pmc_core_mphy_pg_ops = {
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.open = pmc_core_mphy_pg_sts_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int pmc_core_pll_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmcdev = s->private;
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const struct pmc_bit_map *map = pmcdev->map->pll_sts;
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u32 mphy_common_reg, val;
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int index, err = 0;
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if (pmcdev->pmc_xram_read_bit) {
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seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
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return 0;
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}
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mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
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mutex_lock(&pmcdev->lock);
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if (pmc_core_send_msg(&mphy_common_reg) != 0) {
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err = -EBUSY;
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goto out_unlock;
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}
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/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
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msleep(10);
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val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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for (index = 0; map[index].name ; index++) {
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seq_printf(s, "%-32s\tState: %s\n",
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map[index].name,
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map[index].bit_mask & val ? "Active" : "Idle");
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}
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out_unlock:
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mutex_unlock(&pmcdev->lock);
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return err;
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}
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static int pmc_core_pll_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_core_pll_show, inode->i_private);
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}
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static const struct file_operations pmc_core_pll_ops = {
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.open = pmc_core_pll_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
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*userbuf, size_t count, loff_t *ppos)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 val, buf_size, fd;
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int err = 0;
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buf_size = count < 64 ? count : 64;
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mutex_lock(&pmcdev->lock);
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if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
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err = -EFAULT;
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goto out_unlock;
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}
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if (val > NUM_IP_IGN_ALLOWED) {
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err = -EINVAL;
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goto out_unlock;
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}
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fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET);
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fd |= (1U << val);
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pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd);
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out_unlock:
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mutex_unlock(&pmcdev->lock);
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return err == 0 ? count : err;
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}
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static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
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{
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return 0;
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}
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static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
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}
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static const struct file_operations pmc_core_ltr_ignore_ops = {
|
|
.open = pmc_core_ltr_ignore_open,
|
|
.read = seq_read,
|
|
.write = pmc_core_ltr_ignore_write,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|
{
|
|
debugfs_remove_recursive(pmcdev->dbgfs_dir);
|
|
}
|
|
|
|
static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
|
|
{
|
|
struct dentry *dir, *file;
|
|
|
|
dir = debugfs_create_dir("pmc_core", NULL);
|
|
if (!dir)
|
|
return -ENOMEM;
|
|
|
|
pmcdev->dbgfs_dir = dir;
|
|
file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
|
|
dir, pmcdev, &pmc_core_dev_state);
|
|
if (!file)
|
|
goto err;
|
|
|
|
file = debugfs_create_file("pch_ip_power_gating_status",
|
|
S_IFREG | S_IRUGO, dir, pmcdev,
|
|
&pmc_core_ppfear_ops);
|
|
if (!file)
|
|
goto err;
|
|
|
|
file = debugfs_create_file("mphy_core_lanes_power_gating_status",
|
|
S_IFREG | S_IRUGO, dir, pmcdev,
|
|
&pmc_core_mphy_pg_ops);
|
|
if (!file)
|
|
goto err;
|
|
|
|
file = debugfs_create_file("pll_status",
|
|
S_IFREG | S_IRUGO, dir, pmcdev,
|
|
&pmc_core_pll_ops);
|
|
if (!file)
|
|
goto err;
|
|
|
|
file = debugfs_create_file("ltr_ignore",
|
|
S_IFREG | S_IRUGO, dir, pmcdev,
|
|
&pmc_core_ltr_ignore_ops);
|
|
|
|
if (!file)
|
|
goto err;
|
|
|
|
return 0;
|
|
err:
|
|
pmc_core_dbgfs_unregister(pmcdev);
|
|
return -ENODEV;
|
|
}
|
|
#else
|
|
static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|
{
|
|
}
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
static const struct x86_cpu_id intel_pmc_core_ids[] = {
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
{}
|
|
};
|
|
|
|
static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
struct device *ptr_dev = &dev->dev;
|
|
struct pmc_dev *pmcdev = &pmc;
|
|
const struct x86_cpu_id *cpu_id;
|
|
const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
|
|
int err;
|
|
|
|
cpu_id = x86_match_cpu(intel_pmc_core_ids);
|
|
if (!cpu_id) {
|
|
dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = pcim_enable_device(dev);
|
|
if (err < 0) {
|
|
dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
|
|
return err;
|
|
}
|
|
|
|
err = pci_read_config_dword(dev,
|
|
SPT_PMC_BASE_ADDR_OFFSET,
|
|
&pmcdev->base_addr);
|
|
if (err < 0) {
|
|
dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
|
|
return err;
|
|
}
|
|
pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
|
|
dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
|
|
|
|
pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
|
|
pmcdev->base_addr,
|
|
SPT_PMC_MMIO_REG_LEN);
|
|
if (!pmcdev->regbase) {
|
|
dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mutex_init(&pmcdev->lock);
|
|
pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
|
|
pmcdev->map = map;
|
|
|
|
err = pmc_core_dbgfs_register(pmcdev);
|
|
if (err < 0)
|
|
dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
|
|
|
|
pmc.has_slp_s0_res = true;
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_driver intel_pmc_core_driver = {
|
|
.name = "intel_pmc_core",
|
|
.id_table = pmc_pci_ids,
|
|
.probe = pmc_core_probe,
|
|
};
|
|
|
|
builtin_pci_driver(intel_pmc_core_driver);
|