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45df305268
Atomic tests store a DW, but then load it back as a W from the same
address. This doesn't work on big-endian systems, and since the point
of those tests is not testing narrow loads, fix simply by loading a
DW.
Fixes: 98d666d05a ("bpf: Add tests for new BPF atomic operations")
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/bpf/20210210020713.77911-1-iii@linux.ibm.com
77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
{
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"BPF_ATOMIC XOR without fetch",
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.insns = {
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/* val = 0x110; */
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BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
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/* atomic_xor(&val, 0x011); */
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BPF_MOV64_IMM(BPF_REG_1, 0x011),
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BPF_ATOMIC_OP(BPF_DW, BPF_XOR, BPF_REG_10, BPF_REG_1, -8),
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/* if (val != 0x101) exit(2); */
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BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_10, -8),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x101, 2),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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/* r1 should not be clobbered, no BPF_FETCH flag */
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BPF_MOV64_IMM(BPF_REG_0, 0),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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},
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{
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"BPF_ATOMIC XOR with fetch",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, 123),
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/* val = 0x110; */
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BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
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/* old = atomic_fetch_xor(&val, 0x011); */
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BPF_MOV64_IMM(BPF_REG_1, 0x011),
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BPF_ATOMIC_OP(BPF_DW, BPF_XOR | BPF_FETCH, BPF_REG_10, BPF_REG_1, -8),
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/* if (old != 0x110) exit(3); */
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x110, 2),
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BPF_MOV64_IMM(BPF_REG_0, 3),
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BPF_EXIT_INSN(),
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/* if (val != 0x101) exit(2); */
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BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -8),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x101, 2),
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BPF_MOV64_IMM(BPF_REG_1, 2),
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BPF_EXIT_INSN(),
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/* Check R0 wasn't clobbered (fxor fear of x86 JIT bug) */
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 123, 2),
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_EXIT_INSN(),
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/* exit(0); */
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BPF_MOV64_IMM(BPF_REG_0, 0),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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},
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{
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"BPF_ATOMIC XOR with fetch 32bit",
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.insns = {
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/* r0 = (s64) -1 */
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BPF_MOV64_IMM(BPF_REG_0, 0),
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BPF_ALU64_IMM(BPF_SUB, BPF_REG_0, 1),
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/* val = 0x110; */
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BPF_ST_MEM(BPF_W, BPF_REG_10, -4, 0x110),
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/* old = atomic_fetch_xor(&val, 0x011); */
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BPF_MOV32_IMM(BPF_REG_1, 0x011),
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BPF_ATOMIC_OP(BPF_W, BPF_XOR | BPF_FETCH, BPF_REG_10, BPF_REG_1, -4),
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/* if (old != 0x110) exit(3); */
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BPF_JMP32_IMM(BPF_JEQ, BPF_REG_1, 0x110, 2),
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BPF_MOV32_IMM(BPF_REG_0, 3),
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BPF_EXIT_INSN(),
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/* if (val != 0x101) exit(2); */
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BPF_LDX_MEM(BPF_W, BPF_REG_1, BPF_REG_10, -4),
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BPF_JMP32_IMM(BPF_JEQ, BPF_REG_1, 0x101, 2),
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BPF_MOV32_IMM(BPF_REG_1, 2),
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BPF_EXIT_INSN(),
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/* Check R0 wasn't clobbered (fxor fear of x86 JIT bug)
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* It should be -1 so add 1 to get exit code.
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*/
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_0, 1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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},
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