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![Freeman Liu](/assets/img/avatar_default.png)
Add support to the new efuse IP which is integrated in the SC2730 which includes multiple blocks in a single chip. Signed-off-by: Freeman Liu <freeman.liu@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200722100705.7772-5-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
278 lines
7.2 KiB
C
278 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Spreadtrum Communications Inc.
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#include <linux/hwspinlock.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/nvmem-provider.h>
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/* PMIC global registers definition */
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#define SC27XX_MODULE_EN 0xc08
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#define SC2730_MODULE_EN 0x1808
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#define SC27XX_EFUSE_EN BIT(6)
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/* Efuse controller registers definition */
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#define SC27XX_EFUSE_GLB_CTRL 0x0
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#define SC27XX_EFUSE_DATA_RD 0x4
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#define SC27XX_EFUSE_DATA_WR 0x8
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#define SC27XX_EFUSE_BLOCK_INDEX 0xc
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#define SC27XX_EFUSE_MODE_CTRL 0x10
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#define SC27XX_EFUSE_STATUS 0x14
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#define SC27XX_EFUSE_WR_TIMING_CTRL 0x20
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#define SC27XX_EFUSE_RD_TIMING_CTRL 0x24
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#define SC27XX_EFUSE_EFUSE_DEB_CTRL 0x28
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/* Mask definition for SC27XX_EFUSE_BLOCK_INDEX register */
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#define SC27XX_EFUSE_BLOCK_MASK GENMASK(4, 0)
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/* Bits definitions for SC27XX_EFUSE_MODE_CTRL register */
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#define SC27XX_EFUSE_PG_START BIT(0)
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#define SC27XX_EFUSE_RD_START BIT(1)
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#define SC27XX_EFUSE_CLR_RDDONE BIT(2)
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/* Bits definitions for SC27XX_EFUSE_STATUS register */
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#define SC27XX_EFUSE_PGM_BUSY BIT(0)
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#define SC27XX_EFUSE_READ_BUSY BIT(1)
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#define SC27XX_EFUSE_STANDBY BIT(2)
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#define SC27XX_EFUSE_GLOBAL_PROT BIT(3)
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#define SC27XX_EFUSE_RD_DONE BIT(4)
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/* Block number and block width (bytes) definitions */
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#define SC27XX_EFUSE_BLOCK_MAX 32
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#define SC27XX_EFUSE_BLOCK_WIDTH 2
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/* Timeout (ms) for the trylock of hardware spinlocks */
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#define SC27XX_EFUSE_HWLOCK_TIMEOUT 5000
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/* Timeout (us) of polling the status */
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#define SC27XX_EFUSE_POLL_TIMEOUT 3000000
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#define SC27XX_EFUSE_POLL_DELAY_US 10000
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/*
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* Since different PMICs of SC27xx series can have different
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* address , we should save address in the device data structure.
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*/
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struct sc27xx_efuse_variant_data {
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u32 module_en;
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};
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struct sc27xx_efuse {
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struct device *dev;
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struct regmap *regmap;
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struct hwspinlock *hwlock;
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struct mutex mutex;
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u32 base;
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const struct sc27xx_efuse_variant_data *var_data;
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};
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static const struct sc27xx_efuse_variant_data sc2731_edata = {
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.module_en = SC27XX_MODULE_EN,
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};
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static const struct sc27xx_efuse_variant_data sc2730_edata = {
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.module_en = SC2730_MODULE_EN,
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};
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/*
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* On Spreadtrum platform, we have multi-subsystems will access the unique
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* efuse controller, so we need one hardware spinlock to synchronize between
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* the multiple subsystems.
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*/
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static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse)
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{
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int ret;
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mutex_lock(&efuse->mutex);
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ret = hwspin_lock_timeout_raw(efuse->hwlock,
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SC27XX_EFUSE_HWLOCK_TIMEOUT);
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if (ret) {
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dev_err(efuse->dev, "timeout to get the hwspinlock\n");
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mutex_unlock(&efuse->mutex);
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return ret;
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}
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return 0;
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}
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static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse)
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{
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hwspin_unlock_raw(efuse->hwlock);
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mutex_unlock(&efuse->mutex);
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}
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static int sc27xx_efuse_poll_status(struct sc27xx_efuse *efuse, u32 bits)
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{
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int ret;
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u32 val;
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ret = regmap_read_poll_timeout(efuse->regmap,
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efuse->base + SC27XX_EFUSE_STATUS,
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val, (val & bits),
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SC27XX_EFUSE_POLL_DELAY_US,
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SC27XX_EFUSE_POLL_TIMEOUT);
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if (ret) {
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dev_err(efuse->dev, "timeout to update the efuse status\n");
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return ret;
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}
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return 0;
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}
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static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes)
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{
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struct sc27xx_efuse *efuse = context;
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u32 buf, blk_index = offset / SC27XX_EFUSE_BLOCK_WIDTH;
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u32 blk_offset = (offset % SC27XX_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
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int ret;
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if (blk_index > SC27XX_EFUSE_BLOCK_MAX ||
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bytes > SC27XX_EFUSE_BLOCK_WIDTH)
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return -EINVAL;
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ret = sc27xx_efuse_lock(efuse);
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if (ret)
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return ret;
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/* Enable the efuse controller. */
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ret = regmap_update_bits(efuse->regmap, efuse->var_data->module_en,
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SC27XX_EFUSE_EN, SC27XX_EFUSE_EN);
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if (ret)
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goto unlock_efuse;
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/*
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* Before reading, we should ensure the efuse controller is in
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* standby state.
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*/
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ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_STANDBY);
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if (ret)
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goto disable_efuse;
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/* Set the block address to be read. */
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ret = regmap_write(efuse->regmap,
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efuse->base + SC27XX_EFUSE_BLOCK_INDEX,
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blk_index & SC27XX_EFUSE_BLOCK_MASK);
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if (ret)
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goto disable_efuse;
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/* Start reading process from efuse memory. */
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ret = regmap_update_bits(efuse->regmap,
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efuse->base + SC27XX_EFUSE_MODE_CTRL,
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SC27XX_EFUSE_RD_START,
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SC27XX_EFUSE_RD_START);
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if (ret)
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goto disable_efuse;
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/*
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* Polling the read done status to make sure the reading process
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* is completed, that means the data can be read out now.
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*/
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ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_RD_DONE);
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if (ret)
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goto disable_efuse;
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/* Read data from efuse memory. */
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ret = regmap_read(efuse->regmap, efuse->base + SC27XX_EFUSE_DATA_RD,
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&buf);
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if (ret)
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goto disable_efuse;
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/* Clear the read done flag. */
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ret = regmap_update_bits(efuse->regmap,
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efuse->base + SC27XX_EFUSE_MODE_CTRL,
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SC27XX_EFUSE_CLR_RDDONE,
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SC27XX_EFUSE_CLR_RDDONE);
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disable_efuse:
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/* Disable the efuse controller after reading. */
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regmap_update_bits(efuse->regmap, efuse->var_data->module_en, SC27XX_EFUSE_EN, 0);
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unlock_efuse:
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sc27xx_efuse_unlock(efuse);
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if (!ret) {
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buf >>= blk_offset;
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memcpy(val, &buf, bytes);
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}
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return ret;
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}
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static int sc27xx_efuse_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct nvmem_config econfig = { };
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struct nvmem_device *nvmem;
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struct sc27xx_efuse *efuse;
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int ret;
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efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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efuse->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!efuse->regmap) {
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dev_err(&pdev->dev, "failed to get efuse regmap\n");
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return -ENODEV;
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}
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ret = of_property_read_u32(np, "reg", &efuse->base);
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if (ret) {
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dev_err(&pdev->dev, "failed to get efuse base address\n");
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return ret;
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}
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ret = of_hwspin_lock_get_id(np, 0);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to get hwspinlock id\n");
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return ret;
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}
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efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
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if (!efuse->hwlock) {
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dev_err(&pdev->dev, "failed to request hwspinlock\n");
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return -ENXIO;
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}
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mutex_init(&efuse->mutex);
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efuse->dev = &pdev->dev;
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efuse->var_data = of_device_get_match_data(&pdev->dev);
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econfig.stride = 1;
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econfig.word_size = 1;
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econfig.read_only = true;
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econfig.name = "sc27xx-efuse";
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econfig.size = SC27XX_EFUSE_BLOCK_MAX * SC27XX_EFUSE_BLOCK_WIDTH;
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econfig.reg_read = sc27xx_efuse_read;
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econfig.priv = efuse;
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econfig.dev = &pdev->dev;
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nvmem = devm_nvmem_register(&pdev->dev, &econfig);
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if (IS_ERR(nvmem)) {
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dev_err(&pdev->dev, "failed to register nvmem config\n");
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return PTR_ERR(nvmem);
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}
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return 0;
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}
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static const struct of_device_id sc27xx_efuse_of_match[] = {
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{ .compatible = "sprd,sc2731-efuse", .data = &sc2731_edata},
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{ .compatible = "sprd,sc2730-efuse", .data = &sc2730_edata},
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{ }
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};
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static struct platform_driver sc27xx_efuse_driver = {
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.probe = sc27xx_efuse_probe,
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.driver = {
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.name = "sc27xx-efuse",
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.of_match_table = sc27xx_efuse_of_match,
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},
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};
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module_platform_driver(sc27xx_efuse_driver);
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MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
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MODULE_DESCRIPTION("Spreadtrum SC27xx efuse driver");
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MODULE_LICENSE("GPL v2");
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