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![Xingyu Chen](/assets/img/avatar_default.png)
The number of RESET registers and offset of RESET_LEVEL register for Meson-A1 are different from previous SoCs, In order to describe these differences, we introduce the struct meson_reset_param. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Amlogic Meson Reset Controller driver
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/of_device.h>
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#define BITS_PER_REG 32
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struct meson_reset_param {
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int reg_count;
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int level_offset;
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};
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struct meson_reset {
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void __iomem *reg_base;
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const struct meson_reset_param *param;
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struct reset_controller_dev rcdev;
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spinlock_t lock;
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};
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static int meson_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct meson_reset *data =
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container_of(rcdev, struct meson_reset, rcdev);
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unsigned int bank = id / BITS_PER_REG;
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr = data->reg_base + (bank << 2);
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writel(BIT(offset), reg_addr);
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return 0;
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}
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static int meson_reset_level(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct meson_reset *data =
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container_of(rcdev, struct meson_reset, rcdev);
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unsigned int bank = id / BITS_PER_REG;
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr;
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unsigned long flags;
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u32 reg;
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reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(reg_addr);
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if (assert)
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writel(reg & ~BIT(offset), reg_addr);
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else
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writel(reg | BIT(offset), reg_addr);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int meson_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return meson_reset_level(rcdev, id, true);
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}
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static int meson_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return meson_reset_level(rcdev, id, false);
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}
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static const struct reset_control_ops meson_reset_ops = {
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.reset = meson_reset_reset,
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.assert = meson_reset_assert,
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.deassert = meson_reset_deassert,
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};
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static const struct meson_reset_param meson8b_param = {
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.reg_count = 8,
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.level_offset = 0x7c,
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};
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static const struct meson_reset_param meson_a1_param = {
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.reg_count = 3,
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.level_offset = 0x40,
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};
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static const struct of_device_id meson_reset_dt_ids[] = {
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{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
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{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
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{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
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{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
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{ /* sentinel */ },
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};
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static int meson_reset_probe(struct platform_device *pdev)
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{
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struct meson_reset *data;
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struct resource *res;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->reg_base))
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return PTR_ERR(data->reg_base);
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data->param = of_device_get_match_data(&pdev->dev);
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if (!data->param)
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return -ENODEV;
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platform_set_drvdata(pdev, data);
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
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data->rcdev.ops = &meson_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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}
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static struct platform_driver meson_reset_driver = {
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.probe = meson_reset_probe,
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.driver = {
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.name = "meson_reset",
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.of_match_table = meson_reset_dt_ids,
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},
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};
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builtin_platform_driver(meson_reset_driver);
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