linux-stable/drivers/clk/clk-highbank.c
Linus Torvalds 8793422fd9 ACPI and power management updates for 3.9-rc1
- Rework of the ACPI namespace scanning code from Rafael J. Wysocki
   with contributions from Bjorn Helgaas, Jiang Liu, Mika Westerberg,
   Toshi Kani, and Yinghai Lu.
 
 - ACPI power resources handling and ACPI device PM update from
   Rafael J. Wysocki.
 
 - ACPICA update to version 20130117 from Bob Moore and Lv Zheng
   with contributions from Aaron Lu, Chao Guan, Jesper Juhl, and
   Tim Gardner.
 
 - Support for Intel Lynxpoint LPSS from Mika Westerberg.
 
 - cpuidle update from Len Brown including Intel Haswell support, C1
   state for intel_idle, removal of global pm_idle.
 
 - cpuidle fixes and cleanups from Daniel Lezcano.
 
 - cpufreq fixes and cleanups from Viresh Kumar and Fabio Baltieri
   with contributions from Stratos Karafotis and Rickard Andersson.
 
 - Intel P-states driver for Sandy Bridge processors from
   Dirk Brandewie.
 
 - cpufreq driver for Marvell Kirkwood SoCs from Andrew Lunn.
 
 - cpufreq fixes related to ordering issues between acpi-cpufreq and
   powernow-k8 from Borislav Petkov and Matthew Garrett.
 
 - cpufreq support for Calxeda Highbank processors from Mark Langsdorf
   and Rob Herring.
 
 - cpufreq driver for the Freescale i.MX6Q SoC and cpufreq-cpu0 update
   from Shawn Guo.
 
 - cpufreq Exynos fixes and cleanups from Jonghwan Choi, Sachin Kamat,
   and Inderpal Singh.
 
 - Support for "lightweight suspend" from Zhang Rui.
 
 - Removal of the deprecated power trace API from Paul Gortmaker.
 
 - Assorted updates from Andreas Fleig, Colin Ian King,
   Davidlohr Bueso, Joseph Salisbury, Kees Cook, Li Fei,
   Nishanth Menon, ShuoX Liu, Srinivas Pandruvada, Tejun Heo,
   Thomas Renninger, and Yasuaki Ishimatsu.
 
 /
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQIcBAABAgAGBQJRIsArAAoJEKhOf7ml8uNsD6MP/j7C4NA+GTq6RdwoJt+Yki0K
 9Ep8I4pEuRFoN/oskv24EyQhpGJIk6UxWcJ/DWFBc+1VhmKORta7k2Idv/wlJA77
 s7AcDveA9xcDh+TVfbh87TeuiMSXiSdDZbiaQO+wMizWJAF3F84AnjiAqqqyQcSK
 bA5/Siz/vWlt9PyYDaQtHTVE4lpvPuVcQdYewsdaH2PsmUjvIg/TUzg28CTrdyvv
 eHOdBK9R0/OLQLhzRbL0VOGJ//wEl+HJRO0QEhTKPgdQ1e/VH/4Zu5WSzF8P/x4C
 s2f8U4IKQqulDuDHXtpMpelFm7hRWgsOqZLkcyXLs+0dvSM9CTPO6P0ZaImxUctk
 5daHWEsXUnCErDQawt1mcZP8l6qnxofMQIfLXyPVzvlSnHyToTmrtXa1v2u4AuL/
 hOo4MYWsFNUmRdtGFFGlExGgEDZ4G5NwiYjRBl/6XJ3v4nhnnMbuzxP8scpoe5m1
 8tjroJHZFUUs/mFU/H+oRbHzSzXPmp1sddNaTg4OpVmTn3DDh6ljnFhiItd1Ndw0
 5ldVbSe6ETq5RoK0TbzvQOeVpa9F3JfqbrXLQPqfd2iz/No41LQYG1uShRYuXKuA
 wfEcc+c9VMd3FILu05pGwBnU8VS9VbxTYMz7xDxg6b29Ywnb7u+Q1ycCk2gFYtkS
 E2oZDuyewTJxaskzYsNr
 =wijn
 -----END PGP SIGNATURE-----

Merge tag 'pm+acpi-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull ACPI and power management updates from Rafael Wysocki:

 - Rework of the ACPI namespace scanning code from Rafael J.  Wysocki
   with contributions from Bjorn Helgaas, Jiang Liu, Mika Westerberg,
   Toshi Kani, and Yinghai Lu.

 - ACPI power resources handling and ACPI device PM update from Rafael
   J Wysocki.

 - ACPICA update to version 20130117 from Bob Moore and Lv Zheng with
   contributions from Aaron Lu, Chao Guan, Jesper Juhl, and Tim Gardner.

 - Support for Intel Lynxpoint LPSS from Mika Westerberg.

 - cpuidle update from Len Brown including Intel Haswell support, C1
   state for intel_idle, removal of global pm_idle.

 - cpuidle fixes and cleanups from Daniel Lezcano.

 - cpufreq fixes and cleanups from Viresh Kumar and Fabio Baltieri with
   contributions from Stratos Karafotis and Rickard Andersson.

 - Intel P-states driver for Sandy Bridge processors from Dirk
   Brandewie.

 - cpufreq driver for Marvell Kirkwood SoCs from Andrew Lunn.

 - cpufreq fixes related to ordering issues between acpi-cpufreq and
   powernow-k8 from Borislav Petkov and Matthew Garrett.

 - cpufreq support for Calxeda Highbank processors from Mark Langsdorf
   and Rob Herring.

 - cpufreq driver for the Freescale i.MX6Q SoC and cpufreq-cpu0 update
   from Shawn Guo.

 - cpufreq Exynos fixes and cleanups from Jonghwan Choi, Sachin Kamat,
   and Inderpal Singh.

 - Support for "lightweight suspend" from Zhang Rui.

 - Removal of the deprecated power trace API from Paul Gortmaker.

 - Assorted updates from Andreas Fleig, Colin Ian King, Davidlohr Bueso,
   Joseph Salisbury, Kees Cook, Li Fei, Nishanth Menon, ShuoX Liu,
   Srinivas Pandruvada, Tejun Heo, Thomas Renninger, and Yasuaki
   Ishimatsu.

* tag 'pm+acpi-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (267 commits)
  PM idle: remove global declaration of pm_idle
  unicore32 idle: delete stray pm_idle comment
  openrisc idle: delete pm_idle
  mn10300 idle: delete pm_idle
  microblaze idle: delete pm_idle
  m32r idle: delete pm_idle, and other dead idle code
  ia64 idle: delete pm_idle
  cris idle: delete idle and pm_idle
  ARM64 idle: delete pm_idle
  ARM idle: delete pm_idle
  blackfin idle: delete pm_idle
  sparc idle: rename pm_idle to sparc_idle
  sh idle: rename global pm_idle to static sh_idle
  x86 idle: rename global pm_idle to static x86_idle
  APM idle: register apm_cpu_idle via cpuidle
  cpufreq / intel_pstate: Add kernel command line option disable intel_pstate.
  cpufreq / intel_pstate: Change to disallow module build
  tools/power turbostat: display SMI count by default
  intel_idle: export both C1 and C1E
  ACPI / hotplug: Fix concurrency issues and memory leaks
  ...
2013-02-20 11:26:56 -08:00

338 lines
8 KiB
C

/*
* Copyright 2011-2012 Calxeda, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
extern void __iomem *sregs_base;
#define HB_PLL_LOCK_500 0x20000000
#define HB_PLL_LOCK 0x10000000
#define HB_PLL_DIVF_SHIFT 20
#define HB_PLL_DIVF_MASK 0x0ff00000
#define HB_PLL_DIVQ_SHIFT 16
#define HB_PLL_DIVQ_MASK 0x00070000
#define HB_PLL_DIVR_SHIFT 8
#define HB_PLL_DIVR_MASK 0x00001f00
#define HB_PLL_RANGE_SHIFT 4
#define HB_PLL_RANGE_MASK 0x00000070
#define HB_PLL_BYPASS 0x00000008
#define HB_PLL_RESET 0x00000004
#define HB_PLL_EXT_BYPASS 0x00000002
#define HB_PLL_EXT_ENA 0x00000001
#define HB_PLL_VCO_MIN_FREQ 2133000000
#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
#define HB_A9_BCLK_DIV_MASK 0x00000006
#define HB_A9_BCLK_DIV_SHIFT 1
#define HB_A9_PCLK_DIV 0x00000001
struct hb_clk {
struct clk_hw hw;
void __iomem *reg;
char *parent_name;
};
#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
static int clk_pll_prepare(struct clk_hw *hwclk)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 reg;
reg = readl(hbclk->reg);
reg &= ~HB_PLL_RESET;
writel(reg, hbclk->reg);
while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
;
while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
;
return 0;
}
static void clk_pll_unprepare(struct clk_hw *hwclk)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 reg;
reg = readl(hbclk->reg);
reg |= HB_PLL_RESET;
writel(reg, hbclk->reg);
}
static int clk_pll_enable(struct clk_hw *hwclk)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 reg;
reg = readl(hbclk->reg);
reg |= HB_PLL_EXT_ENA;
writel(reg, hbclk->reg);
return 0;
}
static void clk_pll_disable(struct clk_hw *hwclk)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 reg;
reg = readl(hbclk->reg);
reg &= ~HB_PLL_EXT_ENA;
writel(reg, hbclk->reg);
}
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
unsigned long divf, divq, vco_freq, reg;
reg = readl(hbclk->reg);
if (reg & HB_PLL_EXT_BYPASS)
return parent_rate;
divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
vco_freq = parent_rate * (divf + 1);
return vco_freq / (1 << divq);
}
static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
u32 *pdivq, u32 *pdivf)
{
u32 divq, divf;
unsigned long vco_freq;
if (rate < HB_PLL_MIN_FREQ)
rate = HB_PLL_MIN_FREQ;
if (rate > HB_PLL_MAX_FREQ)
rate = HB_PLL_MAX_FREQ;
for (divq = 1; divq <= 6; divq++) {
if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
break;
}
vco_freq = rate * (1 << divq);
divf = (vco_freq + (ref_freq / 2)) / ref_freq;
divf--;
*pdivq = divq;
*pdivf = divf;
}
static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
unsigned long *parent_rate)
{
u32 divq, divf;
unsigned long ref_freq = *parent_rate;
clk_pll_calc(rate, ref_freq, &divq, &divf);
return (ref_freq * (divf + 1)) / (1 << divq);
}
static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 divq, divf;
u32 reg;
clk_pll_calc(rate, parent_rate, &divq, &divf);
reg = readl(hbclk->reg);
if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
/* Need to re-lock PLL, so put it into bypass mode */
reg |= HB_PLL_EXT_BYPASS;
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
writel(reg | HB_PLL_RESET, hbclk->reg);
reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
writel(reg | HB_PLL_RESET, hbclk->reg);
writel(reg, hbclk->reg);
while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
;
while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
;
reg |= HB_PLL_EXT_ENA;
reg &= ~HB_PLL_EXT_BYPASS;
} else {
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
reg &= ~HB_PLL_DIVQ_MASK;
reg |= divq << HB_PLL_DIVQ_SHIFT;
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
}
writel(reg, hbclk->reg);
return 0;
}
static const struct clk_ops clk_pll_ops = {
.prepare = clk_pll_prepare,
.unprepare = clk_pll_unprepare,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
.recalc_rate = clk_pll_recalc_rate,
.round_rate = clk_pll_round_rate,
.set_rate = clk_pll_set_rate,
};
static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
return parent_rate / div;
}
static const struct clk_ops a9periphclk_ops = {
.recalc_rate = clk_cpu_periphclk_recalc_rate,
};
static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
return parent_rate / (div + 2);
}
static const struct clk_ops a9bclk_ops = {
.recalc_rate = clk_cpu_a9bclk_recalc_rate,
};
static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 div;
div = readl(hbclk->reg) & 0x1f;
div++;
div *= 2;
return parent_rate / div;
}
static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
unsigned long *parent_rate)
{
u32 div;
div = *parent_rate / rate;
div++;
div &= ~0x1;
return *parent_rate / div;
}
static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
unsigned long parent_rate)
{
struct hb_clk *hbclk = to_hb_clk(hwclk);
u32 div;
div = parent_rate / rate;
if (div & 0x1)
return -EINVAL;
writel(div >> 1, hbclk->reg);
return 0;
}
static const struct clk_ops periclk_ops = {
.recalc_rate = clk_periclk_recalc_rate,
.round_rate = clk_periclk_round_rate,
.set_rate = clk_periclk_set_rate,
};
static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
{
u32 reg;
struct clk *clk;
struct hb_clk *hb_clk;
const char *clk_name = node->name;
const char *parent_name;
struct clk_init_data init;
int rc;
rc = of_property_read_u32(node, "reg", &reg);
if (WARN_ON(rc))
return NULL;
hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
if (WARN_ON(!hb_clk))
return NULL;
hb_clk->reg = sregs_base + reg;
of_property_read_string(node, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = ops;
init.flags = 0;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
hb_clk->hw.init = &init;
clk = clk_register(NULL, &hb_clk->hw);
if (WARN_ON(IS_ERR(clk))) {
kfree(hb_clk);
return NULL;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
}
static void __init hb_pll_init(struct device_node *node)
{
hb_clk_init(node, &clk_pll_ops);
}
CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
static void __init hb_a9periph_init(struct device_node *node)
{
hb_clk_init(node, &a9periphclk_ops);
}
CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
static void __init hb_a9bus_init(struct device_node *node)
{
struct clk *clk = hb_clk_init(node, &a9bclk_ops);
clk_prepare_enable(clk);
}
CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
static void __init hb_emmc_init(struct device_node *node)
{
hb_clk_init(node, &periclk_ops);
}
CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);