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![Tang Yuantian](/assets/img/avatar_default.png)
The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
280 lines
6.5 KiB
C
280 lines
6.5 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* clock driver for Freescale PowerPC corenet SoCs.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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struct cmux_clk {
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struct clk_hw hw;
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void __iomem *reg;
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u32 flags;
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};
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#define PLL_KILL BIT(31)
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#define CLKSEL_SHIFT 27
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#define CLKSEL_ADJUST BIT(0)
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#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
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static void __iomem *base;
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static unsigned int clocks_per_pll;
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static int cmux_set_parent(struct clk_hw *hw, u8 idx)
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{
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struct cmux_clk *clk = to_cmux_clk(hw);
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u32 clksel;
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clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;
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if (clk->flags & CLKSEL_ADJUST)
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clksel += 8;
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clksel = (clksel & 0xf) << CLKSEL_SHIFT;
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iowrite32be(clksel, clk->reg);
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return 0;
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}
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static u8 cmux_get_parent(struct clk_hw *hw)
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{
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struct cmux_clk *clk = to_cmux_clk(hw);
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u32 clksel;
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clksel = ioread32be(clk->reg);
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clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
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if (clk->flags & CLKSEL_ADJUST)
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clksel -= 8;
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clksel = (clksel >> 2) * clocks_per_pll + clksel % 4;
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return clksel;
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}
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const struct clk_ops cmux_ops = {
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.get_parent = cmux_get_parent,
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.set_parent = cmux_set_parent,
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};
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static void __init core_mux_init(struct device_node *np)
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{
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struct clk *clk;
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struct clk_init_data init;
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struct cmux_clk *cmux_clk;
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struct device_node *node;
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int rc, count, i;
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u32 offset;
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const char *clk_name;
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const char **parent_names;
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rc = of_property_read_u32(np, "reg", &offset);
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if (rc) {
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pr_err("%s: could not get reg property\n", np->name);
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return;
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}
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/* get the input clock source count */
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count = of_property_count_strings(np, "clock-names");
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if (count < 0) {
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pr_err("%s: get clock count error\n", np->name);
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return;
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}
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parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL);
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if (!parent_names) {
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pr_err("%s: could not allocate parent_names\n", __func__);
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return;
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}
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for (i = 0; i < count; i++)
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parent_names[i] = of_clk_get_parent_name(np, i);
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cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);
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if (!cmux_clk) {
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pr_err("%s: could not allocate cmux_clk\n", __func__);
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goto err_name;
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}
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cmux_clk->reg = base + offset;
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node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
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if (node && (offset >= 0x80))
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cmux_clk->flags = CLKSEL_ADJUST;
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rc = of_property_read_string_index(np, "clock-output-names",
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0, &clk_name);
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if (rc) {
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pr_err("%s: read clock names error\n", np->name);
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goto err_clk;
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}
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init.name = clk_name;
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init.ops = &cmux_ops;
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init.parent_names = parent_names;
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init.num_parents = count;
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init.flags = 0;
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cmux_clk->hw.init = &init;
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clk = clk_register(NULL, &cmux_clk->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: could not register clock\n", clk_name);
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goto err_clk;
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}
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rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
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if (rc) {
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pr_err("Could not register clock provider for node:%s\n",
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np->name);
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goto err_clk;
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}
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goto err_name;
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err_clk:
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kfree(cmux_clk);
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err_name:
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/* free *_names because they are reallocated when registered */
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kfree(parent_names);
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}
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static void __init core_pll_init(struct device_node *np)
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{
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u32 offset, mult;
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int i, rc, count;
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const char *clk_name, *parent_name;
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struct clk_onecell_data *onecell_data;
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struct clk **subclks;
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rc = of_property_read_u32(np, "reg", &offset);
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if (rc) {
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pr_err("%s: could not get reg property\n", np->name);
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return;
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}
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/* get the multiple of PLL */
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mult = ioread32be(base + offset);
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/* check if this PLL is disabled */
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if (mult & PLL_KILL) {
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pr_debug("PLL:%s is disabled\n", np->name);
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return;
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}
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mult = (mult >> 1) & 0x3f;
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parent_name = of_clk_get_parent_name(np, 0);
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if (!parent_name) {
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pr_err("PLL: %s must have a parent\n", np->name);
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return;
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}
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count = of_property_count_strings(np, "clock-output-names");
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if (count < 0 || count > 4) {
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pr_err("%s: clock is not supported\n", np->name);
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return;
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}
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/* output clock number per PLL */
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clocks_per_pll = count;
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subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
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if (!subclks) {
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pr_err("%s: could not allocate subclks\n", __func__);
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return;
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}
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onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!onecell_data) {
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pr_err("%s: could not allocate onecell_data\n", __func__);
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goto err_clks;
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}
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for (i = 0; i < count; i++) {
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rc = of_property_read_string_index(np, "clock-output-names",
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i, &clk_name);
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if (rc) {
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pr_err("%s: could not get clock names\n", np->name);
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goto err_cell;
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}
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/*
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* when count == 4, there are 4 output clocks:
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* /1, /2, /3, /4 respectively
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* when count < 4, there are at least 2 output clocks:
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* /1, /2, (/4, if count == 3) respectively.
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*/
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if (count == 4)
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subclks[i] = clk_register_fixed_factor(NULL, clk_name,
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parent_name, 0, mult, 1 + i);
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else
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subclks[i] = clk_register_fixed_factor(NULL, clk_name,
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parent_name, 0, mult, 1 << i);
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if (IS_ERR(subclks[i])) {
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pr_err("%s: could not register clock\n", clk_name);
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goto err_cell;
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}
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}
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onecell_data->clks = subclks;
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onecell_data->clk_num = count;
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rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
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if (rc) {
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pr_err("Could not register clk provider for node:%s\n",
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np->name);
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goto err_cell;
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}
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return;
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err_cell:
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kfree(onecell_data);
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err_clks:
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kfree(subclks);
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}
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static const struct of_device_id clk_match[] __initconst = {
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{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
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{ .compatible = "fsl,core-pll-clock", .data = core_pll_init, },
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{ .compatible = "fsl,core-mux-clock", .data = core_mux_init, },
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{}
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};
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static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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np = pdev->dev.of_node;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(&pdev->dev, "iomap error\n");
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return -ENOMEM;
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}
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of_clk_init(clk_match);
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return 0;
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}
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static const struct of_device_id ppc_clk_ids[] __initconst = {
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{ .compatible = "fsl,qoriq-clockgen-1.0", },
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{ .compatible = "fsl,qoriq-clockgen-2.0", },
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{}
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};
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static struct platform_driver ppc_corenet_clk_driver = {
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.driver = {
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.name = "ppc_corenet_clock",
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.owner = THIS_MODULE,
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.of_match_table = ppc_clk_ids,
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},
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.probe = ppc_corenet_clk_probe,
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};
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static int __init ppc_corenet_clk_init(void)
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{
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return platform_driver_register(&ppc_corenet_clk_driver);
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}
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subsys_initcall(ppc_corenet_clk_init);
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