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![Bill Pemberton](/assets/img/avatar_default.png)
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
371 lines
9.4 KiB
C
371 lines
9.4 KiB
C
/*
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/mfd/pm8xxx/core.h>
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#include <linux/mfd/pm8xxx/irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* PMIC8xxx IRQ */
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#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
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#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
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#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
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#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
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#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
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#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
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#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
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#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
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#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
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#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
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#define PM_IRQF_LVL_SEL 0x01 /* level select */
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#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
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#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
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#define PM_IRQF_CLR 0x08 /* clear interrupt */
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#define PM_IRQF_BITS_MASK 0x70
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#define PM_IRQF_BITS_SHIFT 4
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#define PM_IRQF_WRITE 0x80
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#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
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PM_IRQF_MASK_RE)
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struct pm_irq_chip {
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struct device *dev;
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spinlock_t pm_irq_lock;
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unsigned int devirq;
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unsigned int irq_base;
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unsigned int num_irqs;
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unsigned int num_blocks;
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unsigned int num_masters;
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u8 config[0];
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};
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static int pm8xxx_read_root_irq(const struct pm_irq_chip *chip, u8 *rp)
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{
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return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
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}
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static int pm8xxx_read_master_irq(const struct pm_irq_chip *chip, u8 m, u8 *bp)
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{
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return pm8xxx_readb(chip->dev,
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SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
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}
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static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, u8 bp, u8 *ip)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
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if (rc)
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pr_err("Failed Reading Status rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int pm8xxx_config_irq(struct pm_irq_chip *chip, u8 bp, u8 cp)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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cp |= PM_IRQF_WRITE;
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rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_CONFIG, cp);
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if (rc)
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pr_err("Failed Configuring IRQ rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
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{
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int pmirq, irq, i, ret = 0;
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u8 bits;
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ret = pm8xxx_read_block_irq(chip, block, &bits);
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if (ret) {
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pr_err("Failed reading %d block ret=%d", block, ret);
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return ret;
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}
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if (!bits) {
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pr_err("block bit set in master but no irqs: %d", block);
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return 0;
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}
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/* Check IRQ bits */
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for (i = 0; i < 8; i++) {
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if (bits & (1 << i)) {
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pmirq = block * 8 + i;
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irq = pmirq + chip->irq_base;
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generic_handle_irq(irq);
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}
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}
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return 0;
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}
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static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
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{
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u8 blockbits;
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int block_number, i, ret = 0;
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ret = pm8xxx_read_master_irq(chip, master, &blockbits);
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if (ret) {
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pr_err("Failed to read master %d ret=%d\n", master, ret);
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return ret;
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}
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if (!blockbits) {
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pr_err("master bit set in root but no blocks: %d", master);
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return 0;
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}
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for (i = 0; i < 8; i++)
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if (blockbits & (1 << i)) {
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block_number = master * 8 + i; /* block # */
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ret |= pm8xxx_irq_block_handler(chip, block_number);
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}
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return ret;
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}
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static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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u8 root;
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int i, ret, masters = 0;
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ret = pm8xxx_read_root_irq(chip, &root);
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if (ret) {
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pr_err("Can't read root status ret=%d\n", ret);
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return;
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}
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/* on pm8xxx series masters start from bit 1 of the root */
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masters = root >> 1;
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/* Read allowed masters for blocks. */
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for (i = 0; i < chip->num_masters; i++)
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if (masters & (1 << i))
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pm8xxx_irq_master_handler(chip, i);
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irq_chip->irq_ack(&desc->irq_data);
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}
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static void pm8xxx_irq_mask_ack(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = d->irq - chip->irq_base;
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int master, irq_bit;
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u8 block, config;
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block = pmirq / 8;
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master = block / 8;
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irq_bit = pmirq % 8;
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config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
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pm8xxx_config_irq(chip, block, config);
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}
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static void pm8xxx_irq_unmask(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = d->irq - chip->irq_base;
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int master, irq_bit;
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u8 block, config;
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block = pmirq / 8;
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master = block / 8;
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irq_bit = pmirq % 8;
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config = chip->config[pmirq];
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pm8xxx_config_irq(chip, block, config);
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}
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static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = d->irq - chip->irq_base;
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int master, irq_bit;
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u8 block, config;
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block = pmirq / 8;
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master = block / 8;
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irq_bit = pmirq % 8;
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chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
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| PM_IRQF_MASK_ALL;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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if (flow_type & IRQF_TRIGGER_RISING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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if (flow_type & IRQF_TRIGGER_FALLING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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} else {
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chip->config[pmirq] |= PM_IRQF_LVL_SEL;
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if (flow_type & IRQF_TRIGGER_HIGH)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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else
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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}
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config = chip->config[pmirq] | PM_IRQF_CLR;
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return pm8xxx_config_irq(chip, block, config);
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}
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static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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return 0;
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}
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static struct irq_chip pm8xxx_irq_chip = {
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.name = "pm8xxx",
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.irq_mask_ack = pm8xxx_irq_mask_ack,
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.irq_unmask = pm8xxx_irq_unmask,
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.irq_set_type = pm8xxx_irq_set_type,
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.irq_set_wake = pm8xxx_irq_set_wake,
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.flags = IRQCHIP_MASK_ON_SUSPEND,
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};
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/**
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* pm8xxx_get_irq_stat - get the status of the irq line
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* @chip: pointer to identify a pmic irq controller
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* @irq: the irq number
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*
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* The pm8xxx gpio and mpp rely on the interrupt block to read
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* the values on their pins. This function is to facilitate reading
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* the status of a gpio or an mpp line. The caller has to convert the
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* gpio number to irq number.
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*
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* RETURNS:
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* an int indicating the value read on that line
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*/
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int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
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{
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int pmirq, rc;
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u8 block, bits, bit;
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unsigned long flags;
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if (chip == NULL || irq < chip->irq_base ||
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irq >= chip->irq_base + chip->num_irqs)
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return -EINVAL;
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pmirq = irq - chip->irq_base;
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block = pmirq / 8;
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bit = pmirq % 8;
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spin_lock_irqsave(&chip->pm_irq_lock, flags);
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rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
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if (rc) {
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pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
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irq, pmirq, block, rc);
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goto bail_out;
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}
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rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
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if (rc) {
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pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
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irq, pmirq, block, rc);
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goto bail_out;
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}
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rc = (bits & (1 << bit)) ? 1 : 0;
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bail_out:
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spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pm8xxx_get_irq_stat);
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struct pm_irq_chip * pm8xxx_irq_init(struct device *dev,
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const struct pm8xxx_irq_platform_data *pdata)
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{
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struct pm_irq_chip *chip;
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int devirq, rc;
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unsigned int pmirq;
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if (!pdata) {
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pr_err("No platform data\n");
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return ERR_PTR(-EINVAL);
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}
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devirq = pdata->devirq;
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if (devirq < 0) {
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pr_err("missing devirq\n");
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rc = devirq;
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return ERR_PTR(-EINVAL);
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}
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chip = kzalloc(sizeof(struct pm_irq_chip)
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+ sizeof(u8) * pdata->irq_cdata.nirqs, GFP_KERNEL);
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if (!chip) {
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pr_err("Cannot alloc pm_irq_chip struct\n");
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return ERR_PTR(-EINVAL);
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}
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chip->dev = dev;
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chip->devirq = devirq;
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chip->irq_base = pdata->irq_base;
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chip->num_irqs = pdata->irq_cdata.nirqs;
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chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
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chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
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spin_lock_init(&chip->pm_irq_lock);
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for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
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irq_set_chip_and_handler(chip->irq_base + pmirq,
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&pm8xxx_irq_chip,
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handle_level_irq);
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irq_set_chip_data(chip->irq_base + pmirq, chip);
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#ifdef CONFIG_ARM
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set_irq_flags(chip->irq_base + pmirq, IRQF_VALID);
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#else
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irq_set_noprobe(chip->irq_base + pmirq);
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#endif
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}
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irq_set_irq_type(devirq, pdata->irq_trigger_flag);
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irq_set_handler_data(devirq, chip);
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irq_set_chained_handler(devirq, pm8xxx_irq_handler);
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set_irq_wake(devirq, 1);
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return chip;
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}
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int pm8xxx_irq_exit(struct pm_irq_chip *chip)
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{
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irq_set_chained_handler(chip->devirq, NULL);
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kfree(chip);
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return 0;
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}
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