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![Bill Pemberton](/assets/img/avatar_default.png)
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
466 lines
11 KiB
C
466 lines
11 KiB
C
/*
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* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
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*
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* Copyright (C) 2010 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/wait.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ti_ssp.h>
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/* Register Offsets */
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#define REG_REV 0x00
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#define REG_IOSEL_1 0x04
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#define REG_IOSEL_2 0x08
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#define REG_PREDIV 0x0c
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#define REG_INTR_ST 0x10
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#define REG_INTR_EN 0x14
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#define REG_TEST_CTRL 0x18
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/* Per port registers */
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#define PORT_CFG_2 0x00
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#define PORT_ADDR 0x04
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#define PORT_DATA 0x08
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#define PORT_CFG_1 0x0c
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#define PORT_STATE 0x10
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#define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT)
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#define SSP_PORT_CLKRATE_MASK 0x0f
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#define SSP_SEQRAM_WR_EN BIT(4)
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#define SSP_SEQRAM_RD_EN BIT(5)
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#define SSP_START BIT(15)
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#define SSP_BUSY BIT(10)
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#define SSP_PORT_ASL BIT(7)
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#define SSP_PORT_CFO1 BIT(6)
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#define SSP_PORT_SEQRAM_SIZE 32
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static const int ssp_port_base[] = {0x040, 0x080};
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static const int ssp_port_seqram[] = {0x100, 0x180};
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struct ti_ssp {
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struct resource *res;
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struct device *dev;
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void __iomem *regs;
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spinlock_t lock;
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struct clk *clk;
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int irq;
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wait_queue_head_t wqh;
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/*
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* Some of the iosel2 register bits always read-back as 0, we need to
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* remember these values so that we don't clobber previously set
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* values.
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*/
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u32 iosel2;
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};
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static inline struct ti_ssp *dev_to_ssp(struct device *dev)
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{
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return dev_get_drvdata(dev->parent);
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}
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static inline int dev_to_port(struct device *dev)
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{
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return to_platform_device(dev)->id;
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}
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/* Register Access Helpers, rmw() functions need to run locked */
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static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
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{
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return __raw_readl(ssp->regs + reg);
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}
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static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
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{
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__raw_writel(val, ssp->regs + reg);
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}
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static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
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{
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ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
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}
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static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
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{
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return ssp_read(ssp, ssp_port_base[port] + reg);
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}
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static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
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u32 val)
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{
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ssp_write(ssp, ssp_port_base[port] + reg, val);
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}
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static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
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u32 mask, u32 bits)
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{
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ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
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}
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static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
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u32 bits)
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{
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ssp_port_rmw(ssp, port, reg, bits, 0);
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}
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static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
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u32 bits)
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{
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ssp_port_rmw(ssp, port, reg, 0, bits);
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}
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/* Called to setup port clock mode, caller must hold ssp->lock */
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static int __set_mode(struct ti_ssp *ssp, int port, int mode)
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{
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mode &= SSP_PORT_CONFIG_MASK;
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ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
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return 0;
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}
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int ti_ssp_set_mode(struct device *dev, int mode)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev);
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int ret;
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spin_lock(&ssp->lock);
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ret = __set_mode(ssp, port, mode);
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spin_unlock(&ssp->lock);
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return ret;
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}
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EXPORT_SYMBOL(ti_ssp_set_mode);
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/* Called to setup iosel2, caller must hold ssp->lock */
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static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
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{
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ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
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ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
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}
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/* Called to setup port iosel, caller must hold ssp->lock */
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static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
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{
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unsigned val, shift = port ? 16 : 0;
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/* IOSEL1 gets the least significant 16 bits */
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val = ssp_read(ssp, REG_IOSEL_1);
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val &= 0xffff << (port ? 0 : 16);
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val |= (iosel & 0xffff) << (port ? 16 : 0);
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ssp_write(ssp, REG_IOSEL_1, val);
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/* IOSEL2 gets the most significant 16 bits */
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val = (iosel >> 16) & 0x7;
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__set_iosel2(ssp, 0x7 << shift, val << shift);
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}
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int ti_ssp_set_iosel(struct device *dev, u32 iosel)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev);
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spin_lock(&ssp->lock);
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__set_iosel(ssp, port, iosel);
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spin_unlock(&ssp->lock);
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return 0;
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}
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EXPORT_SYMBOL(ti_ssp_set_iosel);
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int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev);
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int i;
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if (len > SSP_PORT_SEQRAM_SIZE)
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return -ENOSPC;
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spin_lock(&ssp->lock);
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/* Enable SeqRAM access */
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ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
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/* Copy code */
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for (i = 0; i < len; i++) {
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__raw_writel(prog[i], ssp->regs + offs + 4*i +
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ssp_port_seqram[port]);
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}
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/* Disable SeqRAM access */
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ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
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spin_unlock(&ssp->lock);
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return 0;
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}
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EXPORT_SYMBOL(ti_ssp_load);
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int ti_ssp_raw_read(struct device *dev)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev);
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int shift = port ? 27 : 11;
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return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
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}
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EXPORT_SYMBOL(ti_ssp_raw_read);
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int ti_ssp_raw_write(struct device *dev, u32 val)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev), shift;
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spin_lock(&ssp->lock);
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shift = port ? 22 : 6;
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val &= 0xf;
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__set_iosel2(ssp, 0xf << shift, val << shift);
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spin_unlock(&ssp->lock);
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return 0;
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}
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EXPORT_SYMBOL(ti_ssp_raw_write);
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static inline int __xfer_done(struct ti_ssp *ssp, int port)
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{
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return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
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}
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int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output)
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{
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struct ti_ssp *ssp = dev_to_ssp(dev);
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int port = dev_to_port(dev);
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int ret;
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if (pc & ~(0x3f))
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return -EINVAL;
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/* Grab ssp->lock to serialize rmw on ssp registers */
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spin_lock(&ssp->lock);
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ssp_port_write(ssp, port, PORT_ADDR, input >> 16);
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ssp_port_write(ssp, port, PORT_DATA, input & 0xffff);
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ssp_port_rmw(ssp, port, PORT_CFG_1, 0x3f, pc);
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/* grab wait queue head lock to avoid race with the isr */
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spin_lock_irq(&ssp->wqh.lock);
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/* kick off sequence execution in hardware */
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ssp_port_set_bits(ssp, port, PORT_CFG_1, SSP_START);
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/* drop ssp lock; no register writes beyond this */
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spin_unlock(&ssp->lock);
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ret = wait_event_interruptible_locked_irq(ssp->wqh,
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__xfer_done(ssp, port));
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spin_unlock_irq(&ssp->wqh.lock);
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if (ret < 0)
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return ret;
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if (output) {
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*output = (ssp_port_read(ssp, port, PORT_ADDR) << 16) |
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(ssp_port_read(ssp, port, PORT_DATA) & 0xffff);
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}
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ret = ssp_port_read(ssp, port, PORT_STATE) & 0x3f; /* stop address */
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return ret;
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}
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EXPORT_SYMBOL(ti_ssp_run);
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static irqreturn_t ti_ssp_interrupt(int irq, void *dev_data)
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{
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struct ti_ssp *ssp = dev_data;
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spin_lock(&ssp->wqh.lock);
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ssp_write(ssp, REG_INTR_ST, 0x3);
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wake_up_locked(&ssp->wqh);
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spin_unlock(&ssp->wqh.lock);
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return IRQ_HANDLED;
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}
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static int ti_ssp_probe(struct platform_device *pdev)
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{
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static struct ti_ssp *ssp;
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const struct ti_ssp_data *pdata = pdev->dev.platform_data;
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int error = 0, prediv = 0xff, id;
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unsigned long sysclk;
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struct device *dev = &pdev->dev;
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struct mfd_cell cells[2];
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ssp = kzalloc(sizeof(*ssp), GFP_KERNEL);
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if (!ssp) {
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dev_err(dev, "cannot allocate device info\n");
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return -ENOMEM;
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}
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ssp->dev = dev;
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dev_set_drvdata(dev, ssp);
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ssp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!ssp->res) {
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error = -ENODEV;
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dev_err(dev, "cannot determine register area\n");
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goto error_res;
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}
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if (!request_mem_region(ssp->res->start, resource_size(ssp->res),
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pdev->name)) {
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error = -ENOMEM;
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dev_err(dev, "cannot claim register memory\n");
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goto error_res;
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}
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ssp->regs = ioremap(ssp->res->start, resource_size(ssp->res));
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if (!ssp->regs) {
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error = -ENOMEM;
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dev_err(dev, "cannot map register memory\n");
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goto error_map;
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}
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ssp->clk = clk_get(dev, NULL);
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if (IS_ERR(ssp->clk)) {
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error = PTR_ERR(ssp->clk);
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dev_err(dev, "cannot claim device clock\n");
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goto error_clk;
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}
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ssp->irq = platform_get_irq(pdev, 0);
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if (ssp->irq < 0) {
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error = -ENODEV;
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dev_err(dev, "unknown irq\n");
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goto error_irq;
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}
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error = request_threaded_irq(ssp->irq, NULL, ti_ssp_interrupt, 0,
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dev_name(dev), ssp);
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if (error < 0) {
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dev_err(dev, "cannot acquire irq\n");
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goto error_irq;
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}
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spin_lock_init(&ssp->lock);
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init_waitqueue_head(&ssp->wqh);
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/* Power on and initialize SSP */
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error = clk_enable(ssp->clk);
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if (error) {
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dev_err(dev, "cannot enable device clock\n");
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goto error_enable;
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}
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/* Reset registers to a sensible known state */
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ssp_write(ssp, REG_IOSEL_1, 0);
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ssp_write(ssp, REG_IOSEL_2, 0);
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ssp_write(ssp, REG_INTR_EN, 0x3);
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ssp_write(ssp, REG_INTR_ST, 0x3);
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ssp_write(ssp, REG_TEST_CTRL, 0);
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ssp_port_write(ssp, 0, PORT_CFG_1, SSP_PORT_ASL);
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ssp_port_write(ssp, 1, PORT_CFG_1, SSP_PORT_ASL);
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ssp_port_write(ssp, 0, PORT_CFG_2, SSP_PORT_CFO1);
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ssp_port_write(ssp, 1, PORT_CFG_2, SSP_PORT_CFO1);
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sysclk = clk_get_rate(ssp->clk);
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if (pdata && pdata->out_clock)
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prediv = (sysclk / pdata->out_clock) - 1;
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prediv = clamp(prediv, 0, 0xff);
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ssp_rmw(ssp, REG_PREDIV, 0xff, prediv);
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memset(cells, 0, sizeof(cells));
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for (id = 0; id < 2; id++) {
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const struct ti_ssp_dev_data *data = &pdata->dev_data[id];
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cells[id].id = id;
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cells[id].name = data->dev_name;
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cells[id].platform_data = data->pdata;
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cells[id].data_size = data->pdata_size;
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}
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error = mfd_add_devices(dev, 0, cells, 2, NULL, 0, NULL);
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if (error < 0) {
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dev_err(dev, "cannot add mfd cells\n");
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goto error_enable;
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}
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return 0;
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error_enable:
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free_irq(ssp->irq, ssp);
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error_irq:
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clk_put(ssp->clk);
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error_clk:
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iounmap(ssp->regs);
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error_map:
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release_mem_region(ssp->res->start, resource_size(ssp->res));
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error_res:
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kfree(ssp);
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return error;
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}
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static int ti_ssp_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ti_ssp *ssp = dev_get_drvdata(dev);
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mfd_remove_devices(dev);
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clk_disable(ssp->clk);
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free_irq(ssp->irq, ssp);
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clk_put(ssp->clk);
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iounmap(ssp->regs);
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release_mem_region(ssp->res->start, resource_size(ssp->res));
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kfree(ssp);
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dev_set_drvdata(dev, NULL);
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return 0;
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}
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static struct platform_driver ti_ssp_driver = {
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.probe = ti_ssp_probe,
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.remove = ti_ssp_remove,
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.driver = {
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.name = "ti-ssp",
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.owner = THIS_MODULE,
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}
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};
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module_platform_driver(ti_ssp_driver);
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MODULE_DESCRIPTION("Sequencer Serial Port (SSP) Driver");
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MODULE_AUTHOR("Cyril Chemparathy");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:ti-ssp");
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