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![Vitaly Bordug](/assets/img/avatar_default.png)
This covers common CPM access functions, CPM interrupt controller code, micropatch and a few compatibility things to kee the same driver base working with arch/ppc. This version is refined with all the comments (mostly PIC-related) addressed. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
197 lines
4.5 KiB
C
197 lines
4.5 KiB
C
#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/8xx_immap.h>
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#include <asm/mpc8xx.h>
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#include "mpc8xx_pic.h"
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#define PIC_VEC_SPURRIOUS 15
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extern int cpm_get_irq(struct pt_regs *regs);
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static struct device_node *mpc8xx_pic_node;
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static struct irq_host *mpc8xx_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static sysconf8xx_t *siu_reg;
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int cpm_get_irq(struct pt_regs *regs);
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static void mpc8xx_unmask_irq(unsigned int virq)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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}
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static void mpc8xx_mask_irq(unsigned int virq)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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}
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static void mpc8xx_ack(unsigned int virq)
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{
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int bit;
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unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
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bit = irq_nr & 0x1f;
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out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
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}
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static void mpc8xx_end_irq(unsigned int virq)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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}
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static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
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{
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struct irq_desc *desc = get_irq_desc(virq);
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desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
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desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
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if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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desc->status |= IRQ_LEVEL;
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if (flow_type & IRQ_TYPE_EDGE_FALLING) {
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irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq;
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unsigned int siel = in_be32(&siu_reg->sc_siel);
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/* only external IRQ senses are programmable */
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if ((hw & 1) == 0) {
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siel |= (0x80000000 >> hw);
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out_be32(&siu_reg->sc_siel, siel);
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desc->handle_irq = handle_edge_irq;
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}
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}
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return 0;
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}
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static struct irq_chip mpc8xx_pic = {
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.typename = " MPC8XX SIU ",
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.unmask = mpc8xx_unmask_irq,
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.mask = mpc8xx_mask_irq,
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.ack = mpc8xx_ack,
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.eoi = mpc8xx_end_irq,
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.set_type = mpc8xx_set_irq_type,
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};
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unsigned int mpc8xx_get_irq(void)
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{
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int irq;
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/* For MPC8xx, read the SIVEC register and shift the bits down
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* to get the irq number.
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*/
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irq = in_be32(&siu_reg->sc_sivec) >> 26;
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if (irq == PIC_VEC_SPURRIOUS)
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irq = NO_IRQ;
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return irq_linear_revmap(mpc8xx_pic_host, irq);
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}
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static int mpc8xx_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return mpc8xx_pic_node == node;
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}
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static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
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/* Set default irq handle */
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set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
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return 0;
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}
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static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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static unsigned char map_pic_senses[4] = {
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_FALLING,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_pic_senses[intspec[1]];
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else
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static struct irq_host_ops mpc8xx_pic_host_ops = {
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.match = mpc8xx_pic_host_match,
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.map = mpc8xx_pic_host_map,
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.xlate = mpc8xx_pic_host_xlate,
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};
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int mpc8xx_pic_init(void)
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{
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struct resource res;
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struct device_node *np = NULL;
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int ret;
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np = of_find_node_by_type(np, "mpc8xx-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return -ENOMEM;
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}
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mpc8xx_pic_node = of_node_get(np);
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ret = of_address_to_resource(np, 0, &res);
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of_node_put(np);
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if (ret)
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return ret;
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siu_reg = (void *)ioremap(res.start, res.end - res.start + 1);
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if (siu_reg == NULL)
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return -EINVAL;
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mpc8xx_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &mpc8xx_pic_host_ops, 64);
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if (mpc8xx_pic_host == NULL) {
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printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
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ret = -ENOMEM;
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}
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return ret;
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}
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