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235ea828a1
This patch adds the DCB (Data Center Bridging) support for 82599 hardware. This is similar to how the 82598 DCB code works. This patch also removes the BCN (Backwards Congestion Notification) netlink configuration code from the driver. BCN was a pre-standard congestion notification framework, and was not what the IEEE body decided upon for standard congestion management. QCN (802.1Qau), Quantized Congestion Notification is the accepted standard, which is not supported by 82599, hence we remove the support altogether. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
184 lines
5.9 KiB
C
184 lines
5.9 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _DCB_CONFIG_H_
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#define _DCB_CONFIG_H_
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#include "ixgbe_type.h"
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/* DCB data structures */
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#define IXGBE_MAX_PACKET_BUFFERS 8
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#define MAX_USER_PRIORITY 8
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#define MAX_TRAFFIC_CLASS 8
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#define MAX_BW_GROUP 8
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#define BW_PERCENT 100
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#define DCB_TX_CONFIG 0
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#define DCB_RX_CONFIG 1
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/* DCB error Codes */
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#define DCB_SUCCESS 0
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#define DCB_ERR_CONFIG -1
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#define DCB_ERR_PARAM -2
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/* Transmit and receive Errors */
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/* Error in bandwidth group allocation */
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#define DCB_ERR_BW_GROUP -3
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/* Error in traffic class bandwidth allocation */
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#define DCB_ERR_TC_BW -4
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/* Traffic class has both link strict and group strict enabled */
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#define DCB_ERR_LS_GS -5
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/* Link strict traffic class has non zero bandwidth */
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#define DCB_ERR_LS_BW_NONZERO -6
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/* Link strict bandwidth group has non zero bandwidth */
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#define DCB_ERR_LS_BWG_NONZERO -7
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/* Traffic class has zero bandwidth */
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#define DCB_ERR_TC_BW_ZERO -8
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#define DCB_NOT_IMPLEMENTED 0x7FFFFFFF
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struct dcb_pfc_tc_debug {
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u8 tc;
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u8 pause_status;
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u64 pause_quanta;
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};
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enum strict_prio_type {
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prio_none = 0,
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prio_group,
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prio_link
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};
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/* DCB capability definitions */
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#define IXGBE_DCB_PG_SUPPORT 0x00000001
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#define IXGBE_DCB_PFC_SUPPORT 0x00000002
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#define IXGBE_DCB_BCN_SUPPORT 0x00000004
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#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
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#define IXGBE_DCB_GSP_SUPPORT 0x00000010
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#define IXGBE_DCB_8_TC_SUPPORT 0x80
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struct dcb_support {
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/* DCB capabilities */
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u32 capabilities;
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/* Each bit represents a number of TCs configurable in the hw.
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* If 8 traffic classes can be configured, the value is 0x80.
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*/
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u8 traffic_classes;
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u8 pfc_traffic_classes;
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};
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/* Traffic class bandwidth allocation per direction */
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struct tc_bw_alloc {
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u8 bwg_id; /* Bandwidth Group (BWG) ID */
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u8 bwg_percent; /* % of BWG's bandwidth */
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u8 link_percent; /* % of link bandwidth */
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u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
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u16 data_credits_refill; /* Credit refill amount in 64B granularity */
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u16 data_credits_max; /* Max credits for a configured packet buffer
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* in 64B granularity.*/
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enum strict_prio_type prio_type; /* Link or Group Strict Priority */
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};
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enum dcb_pfc_type {
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pfc_disabled = 0,
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pfc_enabled_full,
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pfc_enabled_tx,
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pfc_enabled_rx
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};
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/* Traffic class configuration */
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struct tc_configuration {
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struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
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enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */
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u16 desc_credits_max; /* For Tx Descriptor arbitration */
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u8 tc; /* Traffic class (TC) */
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};
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enum dcb_rx_pba_cfg {
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pba_equal, /* PBA[0-7] each use 64KB FIFO */
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pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
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};
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struct dcb_num_tcs {
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u8 pg_tcs;
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u8 pfc_tcs;
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};
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struct ixgbe_dcb_config {
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struct dcb_support support;
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struct dcb_num_tcs num_tcs;
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struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
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u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
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bool pfc_mode_enable;
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bool round_robin_enable;
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enum dcb_rx_pba_cfg rx_pba_cfg;
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u32 dcb_cfg_version; /* Not used...OS-specific? */
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u32 link_speed; /* For bandwidth allocation validation purpose */
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};
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/* DCB driver APIs */
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/* DCB rule checking function.*/
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s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *config);
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/* DCB credits calculation */
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s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8);
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/* DCB PFC functions */
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s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, struct ixgbe_dcb_config *g);
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s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
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/* DCB traffic class stats */
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s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
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s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
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/* DCB config arbiters */
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s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *, struct ixgbe_dcb_config *);
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/* DCB hw initialization */
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s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
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/* DCB definitions for credit calculation */
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#define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
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#define MINIMUM_CREDIT_REFILL 5 /* 5*64B = 320B */
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#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */
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#define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */
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#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
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#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */
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#endif /* _DCB_CONFIG_H */
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