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91d0ca3d6b
* DSI support for sm8150/sm8250 * Support for per-process GPU pagetables (finally!) for a6xx. There are still some iommu/arm-smmu changes required to enable, without which it will fallback to the current single pgtable state. The first part (ie. what doesn't depend on drm side patches) is queued up for v5.10[1]. * DisplayPort support. Userspace DP compliance tool support is already merged in IGT[2] * The usual assortment of smaller fixes/cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvqjuzH=Po_9EzzFsp2Xq3tqJUTKfsA2g09XY7_+6Ypfw@mail.gmail.com
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
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#include <linux/dma-mapping.h>
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#include "msm_drv.h"
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#include "msm_mmu.h"
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#include "adreno/adreno_gpu.h"
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#include "adreno/a2xx.xml.h"
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struct msm_gpummu {
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struct msm_mmu base;
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struct msm_gpu *gpu;
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dma_addr_t pt_base;
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uint32_t *table;
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};
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#define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base)
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#define GPUMMU_VA_START SZ_16M
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#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
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#define GPUMMU_PAGE_SIZE SZ_4K
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#define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
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static void msm_gpummu_detach(struct msm_mmu *mmu)
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{
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}
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static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
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struct sg_table *sgt, size_t len, int prot)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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struct sg_dma_page_iter dma_iter;
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unsigned prot_bits = 0;
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if (prot & IOMMU_WRITE)
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prot_bits |= 1;
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if (prot & IOMMU_READ)
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prot_bits |= 2;
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for_each_sgtable_dma_page(sgt, &dma_iter, 0) {
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dma_addr_t addr = sg_page_iter_dma_address(&dma_iter);
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int i;
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for (i = 0; i < PAGE_SIZE; i += GPUMMU_PAGE_SIZE)
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gpummu->table[idx++] = (addr + i) | prot_bits;
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}
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/* we can improve by deferring flush for multiple map() */
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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unsigned i;
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for (i = 0; i < len / GPUMMU_PAGE_SIZE; i++, idx++)
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gpummu->table[idx] = 0;
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static void msm_gpummu_destroy(struct msm_mmu *mmu)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
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DMA_ATTR_FORCE_CONTIGUOUS);
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kfree(gpummu);
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}
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static const struct msm_mmu_funcs funcs = {
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.detach = msm_gpummu_detach,
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.map = msm_gpummu_map,
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.unmap = msm_gpummu_unmap,
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.destroy = msm_gpummu_destroy,
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};
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struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
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{
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struct msm_gpummu *gpummu;
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gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
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if (!gpummu)
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return ERR_PTR(-ENOMEM);
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gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base,
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GFP_KERNEL | __GFP_ZERO, DMA_ATTR_FORCE_CONTIGUOUS);
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if (!gpummu->table) {
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kfree(gpummu);
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return ERR_PTR(-ENOMEM);
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}
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gpummu->gpu = gpu;
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msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU);
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return &gpummu->base;
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}
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void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
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dma_addr_t *tran_error)
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{
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dma_addr_t base = to_msm_gpummu(mmu)->pt_base;
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*pt_base = base;
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*tran_error = base + TABLE_SIZE; /* 32-byte aligned */
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}
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